A method for protecting a reconfigurable digital integrated circuit includes multiple parallel processing channels each comprising an instance of a functional logic block and an error detection unit, the method comprising the successive steps of: activating the error detection unit in order to detect an error in at least one processing channel, executing the data replay mechanism, and then activating the error detection unit in order to detect an error in at least one processing channel, if an error is detected again, executing a self-test on each processing channel, for each processing channel, if the self-test does not detect any error, executing the data replay mechanism for this processing channel, if the self-test detects an error, reconfiguring that part of the configuration memory associated with this processing channel.

Integrated circuit devices, systems, and circuitry are provided to perform signal tests on a device under test. One such integrated circuit device may include memory having instructions to generate a number of test streams to send to a device under test and a testbench processor. The testbench processor may generate the test streams based on the instructions using thread execution circuitry that switches context based on context identifiers corresponding to respective test streams.

A method may involve applying, by a testing computing device, a distortion to a computing device under test. The distortion includes operating the computing device under test at a performance range of a computational resource that could cause the computing device under test to operate outside a normal range. The method may also involve receiving, by the testing computing device and in response to the applying of the distortion, one or more digital signals from the computing device under test. The method may further involve comparing, by the testing computing device, the one or more digital signals to one or more baseline digital signals associated with the computing device under test. The method may also involve detecting, based on the comparing, a presence of at least one anomalous element that could be indicative of a hostile element in the computing device under test.

A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

The present disclosure relates to a measurement system for a parallel measurement with multiple tones, comprising: an RF signal source being configured to generate a continuous wave, CW, signal having at least two CW tones, the RF signal source being configured to feed said CW signal to an output port of the system which is arranged for being connected to a device-under-test, DUT; an input port being arranged to receive a response signal from the DUT, the response signal having at least two tones which are based on the at least two CW tones; a conversion unit being configured to convert the response signal to an intermediate frequency, IF, signal by means of analog mixing, thereby converting the at least two tones of the response signal to at least two IF tones; an analog-to-digital converter being configured to convert the IF signal to a digital signal; a parallel processing unit being configured to isolate the at least two IF tones of the IF signal using a digital down conversion, DDC, technique; the parallel processing unit being further configured to perform a measurement on the at least two CW tones and the at least two IF tones to determine at least one scattering parameter of the DUT.

A method for measuring (and controlling) a characteristic performance parameter Γ.sub.s of a device under test (DUT) having an input port (at the minimum). The method involves connecting the input port of the DUT to a signal generator, subjecting the DUT to a large signal input test signal, and executing a first measurement of the incident wave and reflected wave at a DUT input reference plane. The method further involves subjecting the DUT to a perturbation signal combined with the large signal input test signal, and executing a second measurement of the incident wave and reflected wave at the DUT input reference plane, and determining the characteristic performance parameter from the first measurement and the second measurement.

A test and measurement device includes an input for receiving a test waveform from a Device Under Test (DUT), where the test waveform has a plurality of input level transitions, a selector structured to respectively and individually extract only those portions of the test waveform that match two or more predefined patterns of input level transitions of the test waveform, a noise compensator structured to individually determine and remove, for each of the extracted portions of the waveform, a component of a jitter measurement caused by random noise of the test and measurement device receiving the test waveform, a summer structured to produce a composite distribution of timing measurements with removed noise components from the extracted portions of the test waveform, and a jitter processor structured to determine a first noise-compensated jitter measurement of the DUT from the composite distribution. Methods of determining noise-compensated jitter measurements are also disclosed.

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

The present invention relates to a self-diagnostic apparatus capable of improving safety of a device under test (DUT) by analyzing a characteristic change of a DUT, such as a semiconductor, a circuit module, or a system, in a safe operating region over time and allowing a regular test and a periodic test to be performed even while the DUT is running.