A method for determining a patterning device pattern. The method includes obtaining (i) an initial patterning device pattern having at least one feature, and (ii) a desired feature size of the at least one feature, obtaining, based on a patterning process model, the initial patterning device pattern and a target pattern for a substrate, a difference value between a predicted pattern of the substrate image by the initial patterning device and the target pattern for the substrate, determining a penalty value related the manufacturability of the at least one feature, wherein the penalty value varies as a function of the size of the at least one feature, and determining the patterning device pattern based on the initial patterning device pattern and the desired feature size such that a sum of the difference value and the penalty value is reduced.

A method of determining a mask pattern for a target pattern to be printed on a substrate. The method includes partitioning a portion of a design layout including the target pattern into a plurality of cells with reference to a given location on the target pattern; assigning a plurality of variables within a particular cell of the plurality of cells, the particular cell including the target pattern or a portion thereof; and determining, based on values of the plurality of variables, the mask pattern for the target pattern such that a performance metric of a patterning process utilizing the mask pattern is within a desired performance range.

A lithography process is described by a design for a lithographic mask and a description of the lithography configuration, which may include the lithography source, collection/illumination optics, projection optics, resist, and/or subsequent fabrication steps. The actual lithography process uses a lithographic mask fabricated from the mask design, which may be different than the nominal mask design. A mask fabrication model models the process for fabricating the lithographic mask from the mask design. Typically, this is an electron-beam (e-beam) process, which includes e-beam exposure of resist on a mask blank, processing of the exposed resist to form patterned resist, and etching of the mask blank with the patterned resist. The mask fabrication model, usually in conjunction with other process models, is used to estimate a result of the lithography process. Mask correction is then applied to the mask design based on the simulation result.

Enhancing target features of a pattern imaged onto a substrate. This may include adding one or more assist features to a patterning device pattern in one or more locations adjacent to one or more target features in the patterning device pattern. The one or more assist features are added based on two or more different focus positions in the substrate. This can also include shifting the patterning device pattern and/or a design layout based on the two or more different focus positions and the one or more added assist features. This may be useful for improving across slit asymmetry. Adding the one or more assist features to the pattern and shifting the pattern and/or the design layout enhances the target features by reducing a shift caused by across slit asymmetry for a slit of a multifocal lithographic imaging apparatus. This may reduce the shift across an entire imaging field.

An optical proximity correction method includes designing a mask design. The designing of the mask design includes setting a reference point of the mask design, calculating a plurality of chief ray angles of a plurality of points of interest on the mask design, respectively, each of the plurality of points of interest having a corresponding distance from the reference point, finding, among the plurality of points of interest, a first point of interest having a maximum chief ray angle among the plurality of chief ray angles, a distance of the first point of interest from the reference point being set as a deteriorated distance, and compensating for distortion of an image to be transferred from a pattern located at the deteriorated distance from the reference point of the mask design.

A method to improve a lithographic process of imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method including: computing a multi-variable cost function, the multi-variable cost function being a function of a stochastic variation of a characteristic of an aerial image or a resist image, or a function of a variable that is a function of the stochastic variation or that affects the stochastic variation, the stochastic variation being a function of a plurality of design variables that represent characteristics of the lithographic process; and reconfiguring one or more of the characteristics of the lithographic process by adjusting one or more of the design variables until a certain termination condition is satisfied.

The present application discloses an OPC model simulation method. The method includes the following steps: step 1, establishing a precision judgment function which is formed by multiplying each square of the difference between a simulation point of an OPC model and an actual point on a wafer, by weight, and then superposing all the squares; step 2, performing random data sampling, comprising forming distributed computing nodes; randomly distributing data to each computing node, and meanwhile distributing a current state value of fitting parameter space composed of all fitting parameters to each computing node; computing a local precision judgment function of each computing node; step 3, performing parallel computing to obtain the gradient of each local precision judgment function, and computing a first derivative and a first order approximate value of the gradient of each local precision judgment function; step 4, performing gradient composition and iteration.

Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.

A method including: obtaining data based an optical proximity correction for a spatially shifted version of a training design pattern; and training a machine learning model configured to predict optical proximity corrections for design patterns using data regarding the training design pattern and the data based on the optical proximity correction for the spatially shifted version of the training design pattern.

This application discloses a computing system to identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data and to generate process windows for the identified structures based, at least in part, on the mask layout data and a failure definition for the identified structures. The computing system utilizes process windows for the identified structures to determine failure rates for the identified structures based on a distribution of the manufacturing parameters. The computing system determines frequency of occurrences for the identified structures from the mask layout data and generates a die yield metric for the integrated circuit by aggregating the failure rates for the identified structures based on the frequency of occurrences for the identified structures in the integrated circuit. These increases in yield of the integrated circuit allow manufacturers to produce more units per fixed processing cost of the wafer.