Systems, methods, and apparatus improve synchronization of trigger timing when triggers are configured over a serial bus. A data communication apparatus has an interface circuit that couples the data communication apparatus to a serial bus and is configured to receive a clock signal from the serial bus, a plurality of counters configured to count pulses in the clock signal, and a controller configured to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to the plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the counters to refrain from counting until all of the counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero.

An information processing apparatus includes: an interface unit that communicates with another device through a plurality of physical links; a setting unit that determines a value of a setting parameter for setting a signal transmission characteristic for each of the plurality of physical links by performing a negotiation with the other device and that outputs a plurality of determined values of the setting parameter, each of the plurality of determined values corresponding to one of the plurality of physical links; and a judgment unit that judges whether each of the plurality of determined values is correct or not by judging whether or not a difference between a maximum value and a minimum value among the plurality of determined values falls within a predetermined range.

An apparatus includes a plurality of output ports and a processor. The output ports may each be configured to connect to a respective trigger device and generate an output signal to activate the respective trigger device. The processor may be configured to determine a number of the trigger devices connected to the output ports, determine a timing between each of the number of the trigger devices connected, convert the timing for each of the trigger devices to fit a standard timing using offset values specific to each of the trigger devices and perform a trigger routine to trigger the output signal for each of the trigger devices connected. The trigger routine may activate each of the trigger devices connected according to an event. The offset values may delay triggering the trigger devices to ensure that the trigger devices are sequentially activated at intervals that correspond consistently with the standard timing.

A dynamic bus communication apparatus for an electrosurgical system includes a data wire, a clock wire, a first variable resistor coupled to the data wire, a second variable resistor coupled to the clock wire, an analog to digital converter (ADC), and a controller. The data wire is configured to transmit a data signal between a battery and an instrument powered by the battery. The clock wire is configured to transmit a clock signal between a battery and an instrument. The ADC is configured to sample the data signal and the clock signal at a substantially higher frequency than a frequency of the clock signal. The controller is configured to control a resistance of the first variable resistor and a resistance of the second variable resistor based on the digitally sampled data signal and the digitally sampled clock signal.

An apparatus includes a plurality of output ports and a processor. The output ports may each be configured to connect to a respective trigger device and generate an output signal to activate the respective trigger device. The processor may be configured to determine a number of the trigger devices connected to the output ports, determine a timing between each of the number of the trigger devices connected, convert the timing for each of the trigger devices to fit a standard timing using offset values specific to each of the trigger devices and perform a trigger routine to trigger the output signal for each of the trigger devices connected. The trigger routine may activate each of the trigger devices connected according to an event. The offset values may delay triggering the trigger devices to ensure that the trigger devices are sequentially activated at intervals that correspond consistently with the standard timing.

An integrated-circuit device comprises a source register in a reset domain, a destination circuit outside the reset domain, and a reset checking circuit. The checking circuit comprises a buffer outside the reset domain for receiving data values output by the source register, a reset detector, and reset checking logic. The checking logic detects a new data value output by the source register, checks whether a reset of the reset domain has been detected, and contingently outputs a control signal for controlling whether the destination circuit receives the new data value from the buffer. The reset detector signals whether a reset has been detected by using a feedback path to hold a predetermined value in a resettable latch until the latch receives a reset signal, and to hold a different value in the latch after receiving a reset signal.

An apparatus includes a plurality of output ports and a processor. The output ports may each be configured to connect to a respective trigger device and generate an output signal to activate the respective trigger device. The processor may be configured to determine a number of the trigger devices connected to the output ports, determine a timing between each of the number of the trigger devices connected, convert the timing for each of the trigger devices to fit a standard timing using offset values specific to each of the trigger devices and perform a trigger routine to trigger the output signal for each of the trigger devices connected. The trigger routine may activate each of the trigger devices connected according to an event. The offset values may delay triggering the trigger devices to ensure that the trigger devices are sequentially activated at intervals that correspond consistently with the standard timing.

A processing and storage circuit includes an internal bus, one or more first-level internal memory units, a central processing unit (CPU), one or more hardware acceleration engines, and an arbiter. The first-level internal memory unit is coupled to the internal bus. The CPU includes a second-level internal memory unit, and is configured to access the first-level internal memory unit via the internal bus, and when the CPU accesses data, the first-level internal memory unit is accessed preferentially. The hardware acceleration engine is configured to access the first-level internal memory unit via the internal bus. The arbiter is coupled to the internal bus, configured to decide whether the CPU or the hardware acceleration engine be allowed to access the first-level internal memory unit. The arbiter sets the priority of the CPU accessing the first-level internal memory unit to be over the hardware acceleration engine.

A read command is issued to initiate a transfer of diagnostic information from a communication component of the computing environment. Based on issuing the read command, the diagnostic information is obtained from the communication component. The diagnostic information is configured based on a version of diagnostic information requested. The version is one version of a plurality of versions to be supported by the communication component. The diagnostic information includes diagnostic information relating to one or more communication components of the computing environment and to be used to facilitate communication within the computing environment.

A method of transferring data from a first bus to a second bus across an asynchronous interface using an asynchronous bridge. The bridge comprises a bus slave module, connected to the first bus, comprising a forward-channel initiator in a first power and/or clock domain; and a bus master module, connected to the second bus, comprising a forward-channel terminator in a second power and/or clock domain. The forward-channel initiator and terminator are in communication to form a forward lockable mutex for arbitrating access to signals used to transfer data from the first domain to the second domain. If the mutex is locked, a forward data channel is used to transfer data between the domains. Otherwise if the mutex is unlocked, the forward channel initiator toggles a status request signal and the forward channel terminator toggles a status acknowledge signal in response, the mutex thereby becoming locked.