A data bus subscriber and a method for processing data, wherein the data bus subscriber can be connected to a local bus, particularly a ring bus, and the data bus subscriber has an input interface, which can be connected to the local bus, for receiving first local bus data, an output interface, which can be connected to the local bus, for transmitting second local bus data, a processing component for synchronous processing of the first local bus data and/or data stored in a memory and for output of at least one control signal, a logic unit, which is adapted in order to modify a quantity of received first local bus data based on the control signal in order to generate the second local bus data to be transmitted, wherein the logic unit is further adapted for synchronous, delayed transmitting of the second local bus data via the output interface.

An event recorder for a power supply and a method thereof are provided. The event recorder method includes: selecting an event combination; based on the selected event combination, performing a setting step to set a trigger source combination and a record data combination, wherein the setting step further comprises any combination of the following: setting a record data type combination, setting a trigger type combination, setting a resolution combination, and setting a logic combination; and in response to a logic combination result of the trigger source combination, storing the record data combination in a storage unit.

The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Disclosed is an Avalon-to-Axi4 bus conversion method, including: in case that an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, performing a logical process on the received Avalon_st bus data, and then outputting corresponding Axi4_st bus data; and in case that the Avalon bus is an Avalon_mm bus, receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus.

A method for controlling the sending of data by a plurality of processors belonging to a device, the method comprising: sending a first message to a first processor of the plurality of processors to grant permission to the first processor of the plurality of processors to send a first set of data packets over at least one external interface of the device; receiving from the first processor, an identifier of a second processor of the plurality of processors; and in response to receipt of the identifier of the second processor, send a second message to the second processor to grant permission to the second processor to send a second set of data packets over the at least one external interface.

Isochronous channels may be used for transporting non-isochronous data between components in an electronic device, such as when non-isochronous data is aggregated from multiple non-isochronous data streams to achieve a high peak-to-average bandwidth. The aggregated non-isochronous data sources may include data streams from general-purpose communications interfaces for interconnecting components or sub-systems of components within an electronic device. For example, I2C networks for control and programming of components may be connected to other I2C networks through an isochronous channel, such as a differential pair of Soundwire SWI3S wires.

The controller is configured to receive commands from a host device through a PCIe bus having a MAC, send data to the host device through the PCIe bus, and execute a function level reset (FLR) command. The controller includes a direct memory access (DMA) unit and either a drain unit or a drain and drop unit coupled between the DMA and the PCIe bus. The units are configured to prevent transactions associated with the FLR command to pass from the DMA to the MAC during execution of the FLR command, where the preventing transactions comprises receiving a request from the DMA, storing the request in a pipe, removing the request from the pipe, and providing a response to the DMA without delivering the request to the MAC. The drain and drop unit is configured to drop a MAC generated response.

Techniques for transmitting data include identifying data to be transmitted, adding the data to a queue, and in response to a data session window being open: extracting the data from the queue; transmitting the extracted data to a transceiver via a transmitter; monitoring an amount of data in the queue and determining that the transmitter has transmitted the extracted data to the transceiver; and in response, instructing the transceiver to end the data session window early and transition to a lower power state.

Techniques for transmitting data include identifying data to be transmitted; and in response to a data session window being open: transmitting the data to a transceiver via a transmitter; determining whether there is additional data to be transmitted and determining whether the transmitter has transmitted the data to the transceiver; and in response, instructing the transceiver to end the data session window early and transition to a lower power state.

An integrated circuit is described. This integrated circuit may include: an interface module with a first power domain and a second power domain. The first power domain may include a digital controller, and the second power domain may include a first analog front end (AFE) circuit. Moreover, the interface module may include up/down level shifters that communicate electrical signals that include a DC component from the first power domain to the second power domain. In some embodiments, the integrated circuit may provide a fully on-chip solution to handle level shifting between the AFE circuit and a digital controller in Universal Serial Bus (USB) 2.0 during communication of electrical signals in a full-speed mode and/or a high-speed mode.