A chip part is provided that includes a substrate in which an element region and an electrode region are set, an insulating film (a first insulating film and a second insulating film) which is formed on the substrate and which selectively includes an internal concave/convex structure in the electrode region on a surface, a first connection electrode and a second connection electrode which include, at a bottom portion, an anchor portion entering the concave portion of the internal concave/convex structure and which include an external concave/convex structure on a surface on the opposite side and a circuit element which is disposed in the element region and which is electrically connected to the first connection electrode and the second connection electrode.

An amplifier receives an input and a feedback. A first transistor controlled by the amplifier output is coupled between a supply node and the feedback. A second transistor controlled by the amplifier output is coupled to the supply node and generates a bias current. A trimmed resistor coupled between the feedback and ground includes, for trimming resolution of N-bits, where X+Y=N: M resistors, where M=2.sup.X−1, each having a resistance equal to R*(2.sup.Y)*i, i being an index having a value ranging from 1 to 2.sup.X−1, a first of the M resistors having a resistance of R*2.sup.Y, a last of the M resistors having a resistance of R*2.sup.Y*(2.sup.X−1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.

A chip part is provided that includes a substrate 2 in which an element region 5 and an electrode region 16 are set, an insulating film (a first insulating film 9 and a second insulating film 3) which is formed on the substrate 2 and which selectively includes an internal concave/convex structure 18 in the electrode region 16 on a surface, a first connection electrode 3 and a second connection electrode 4 which include, at a bottom portion, an anchor portion 24 entering the concave portion 17 of the internal concave/convex structure 18 and which include an external concave/convex structure 6, 7 on a surface on the opposite side and a circuit element which is disposed in the element region 5 and which is electrically connected to the first connection electrode 3 and the second connection electrode 4.

An amplifier receives an input and a feedback. A first transistor controlled by the amplifier output is coupled between a supply node and the feedback. A second transistor controlled by the amplifier output is coupled to the supply node and generates a bias current. A trimmed resistor coupled between the feedback and ground includes, for trimming resolution of N-bits, where X+Y=N: M resistors, where M=2.sup.X−1, each having a resistance equal to R*(2.sup.Y)*i, i being an index having a value ranging from 1 to 2.sup.X−1, a first of the M resistors having a resistance of R*2.sup.Y, a last of the M resistors having a resistance of R*2.sup.Y*(2.sup.X−1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.

An electrical resistor element, system, and method related thereto, wherein the electrical resistor element includes a tunable resistance. The electrical resistor element comprises a first contact electrode, a second contact electrode and a ferroelectric layer arranged between the first contact electrode and the second contact electrode. The ferroelectric layer comprises a first area having a first polarization direction and a second area having a second polarization direction. The first polarization direction is different to the second polarization direction. The ferroelectric layer further comprises a domain wall between the first area and the second area. The electrical resistor element further comprises a first pinning element configured to stabilize the first polarization direction of the ferroelectric layer. The electrical resistor element further comprises a control circuit configured to tune the resistance of the electrical resistor element by applying electrical pulses to the ferroelectric layer such that the ferroelectric domain wall is moved.

A chip part is provided that includes a substrate in which an element region and an electrode region are set, an insulating film (a first insulating film and a second insulating film) which is formed on the substrate and which selectively includes an internal concave/convex structure in the electrode region on a surface, a first connection electrode and a second connection electrode which include, at a bottom portion, an anchor portion entering the concave portion of the internal concave/convex structure and which include an external concave/convex structure on a surface on the opposite side and a circuit element which is disposed in the element region and which is electrically connected to the first connection electrode and the second connection electrode.

A resistance trimming circuit has a resolution of N=X+Y bits. Included is a first circuit with M resistors, where M=2.sup.X1, with each of the M resistors having a resistance of R*(2.sup.Y)*i, i being an index having a value ranging from 1 to 2.sup.X1. M switches are associated with the M resistors. Each of the M resistors is coupled between a first node and its one of the M switches, and each of the M switches couples its one of the M resistors to a second node. Included is a second circuit with P resistors, where P=2.sup.Y1, with each of the P resistors having a resistance of R*i. P switches are associated with the P resistors. Each of the P resistors is coupled between the second node and its one of the P switches, and each of the P switches selectively couples its one of the P resistors to a third node.

A circuit and method provide improved trimming of a DCR sensing circuit where a sensing element is sensitive to self-heating or having a large tolerance. The circuit includes a resistive divider circuit coupled to a sensing element. The resistive divider circuit includes a trim resistor and two test points. Prior to trimming the trim resistor, an actual resistance of the sensing element is determined. A target voltage across the trim resistor to be trimmed is calculated according to the determined sensing element resistance and a known small trim current that is to be injected into the circuit during the trimming process. This injected trim current has a low current value so there is no self-heating of the sensing element. Then, the trim resistor is trimmed while injecting this small trim current into the resistive divider circuit and the voltage across the trim resistor is monitored.

An electrical resistor element, system, and method related thereto, wherein the electrical resistor element includes a tunable resistance. The electrical resistor element comprises a first contact electrode, a second contact electrode and a ferroelectric layer arranged between the first contact electrode and the second contact electrode. The ferroelectric layer comprises a first area having a first polarization direction and a second area having a second polarization direction. The first polarization direction is different to the second polarization direction. The ferroelectric layer further comprises a domain wall between the first area and the second area. The electrical resistor element further comprises a first pinning element configured to stabilize the first polarization direction of the ferroelectric layer. The electrical resistor element further comprises a control circuit configured to tune the resistance of the electrical resistor element by applying electrical pulses to the ferroelectric layer such that the ferroelectric domain wall is moved.

Embodiments include methods, computer systems and computer program products for controlling resistance value of a resistor in a circuit. Aspects include: retrieving, via a controller, a set of parameters of the resistor from a non-volatile memory in the circuit, detecting, via the controller, an operating temperature of the resistor during circuit operation in field using a temperature sensor, generating, by the controller, a temperature difference between operating temperature detected and a target temperature at which the resistor has a target resistance value, producing, by the controller, a control signal responsive to the temperature difference generated, and transmitting the control signal to a temperature regulator placed adjacent to the resistor to adjust the resistance value of the resistor. Resistance value of resistor varies in response to temperature changes around resistor according to a temperature coefficient of the resistance of the resistor. The temperature regulator may include a precision resistive heater.