A method of manufacturing a semiconductor element includes formation of a modified layer, detection of a first region, and cutting of a semiconductor wafer. In the formation of the modified layer, a laser is irradiated on the semiconductor wafer to form the modified layer extending along a surface of the semiconductor wafer inside the semiconductor wafer. The surface of the semiconductor wafer includes a peripheral portion having the first region and a second region. The first region is a region in which the modified layer is not located, and the second region is a region in which the modified layer is formed. In the cutting of the semiconductor wafer, the semiconductor wafer is cut at the modified layer starting from the second region.

A wafer having a semiconductor substrate including a peripheral region and a central region, an insulating layer and a semiconductor layer is prepared first. Next, a plurality of trenches penetrating through the semiconductor layer and the insulating layer and reaching an inside of the semiconductor substrate are formed. Next, an inside of each of the plurality of trenches is filled with an insulating film, so that a plurality of element isolating portions is formed. Next, in the central region, the semiconductor layer exposed from a resist pattern is removed. The end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for removing the semiconductor layer in the central region is formed so as to be positioned closer to the outer edge of the semiconductor substrate than a position of the end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for forming the trenches.

The embodiments of the present disclosure relate to a packaging method, a panel assembly, a wafer package and a chip package. The semiconductor device packaging method includes: providing at least one wafer including a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, the first surface being an active surface; forming a connection portion on the side surface of the at least one wafer around the wafer, the wafer and the connection portion forming a panel assembly, the connection portion includes a third surface on the same side of the first surface of the wafer and a fourth surface on the same side as the second surface of the wafer, the third surface and the first surface forming a to-be-processed surface of the panel assembly; and forming a first dielectric layer on the first surface of the wafer. The packaging method of the embodiments of the present disclosure may improve packaging efficiency and utilization of a wafer.

Energy is locally supplied to a cutting surface that is formed in an outer circumferential region of a wafer in a trimming step, before a grinding step of grinding the wafer. This can remove or repair at least part of a damage layer formed in the outer circumferential region of the wafer due to the trimming step. As a result, breakage of the wafer that originates from the outer circumferential region in the grinding of the wafer which has been subjected to the edge trimming and generation of dust in a step after this grinding can be suppressed.

A method of separating a wafer into at least two thinner wafers includes a pressing member placing step of placing a pressing member that is transmissive of a wavelength of a laser beam on a first surface of the wafer such that the pressing member is pressed against the first surface of the wafer, a separation initiating point forming step of forming a separation initiating point in the wafer by applying the laser beam whose wavelength is transmittable through the wafer to the wafer while positioning a focused spot of the laser beam within the wafer and moving the focused spot and the wafer relatively to each other along a first direction, and an indexing feed step of moving the focused spot and the wafer relatively to each other along a second direction perpendicular to the first direction.

An apparatus for semiconductor manufacturing includes an input port to receive a carrier, wherein the carrier includes a carrier body, a housing installed onto the carrier body, and a filter installed between the carrier body and the housing. The apparatus further includes a first robotic arm to uninstall the housing from the carrier and to reinstall the housing into the carrier; one or more second robotic arms to remove the filter from the carrier and to install a new filter into the carrier; and an output port to release the carrier to production.

A semiconductor wafer manufacturing method including: forming a plurality of trench capacitors at a main surface of a semiconductor wafer, wherein each of the plurality of trench capacitors is configured as unit cells that internally include unit trench capacitors, and wherein a length component in a predetermined direction of a layout pattern of trenches of the plurality of trench capacitors is made equivalent, within a fixed tolerance range, to a length component in a direction that intersects the predetermined direction.

The cleaning apparatus includes multiple kinds of cleaning modules each configured to perform a cleaning processing of a substrate, a first accommodating section configured to accommodate the multiple kinds of cleaning modules therein, and a fluid supply section configured to supply a fluid to the cleaning modules accommodated in the first accommodating section through a pipe. Each of the multiple kinds of cleaning modules includes a pipe connection portion having a common connection position to be connected with the pipe.

A method of increasing the resistivity of a silicon carbide wafer includes providing a silicon carbide wafer with a first resistivity, and applying a microwave to treat the silicon carbide wafer. The treated silicon carbide wafer has a second resistivity. The second resistivity is higher than the first resistivity. The microwave treated silicon carbide wafer can be applied in a high-frequency device.

A system includes a plurality of semiconductor processing tools; a carrier purge station; a carrier repair station; and an overhead transport (OHT) loop for transporting one or more substrate carriers among the plurality of semiconductor processing tools, the carrier purge station, and the carrier repair station. The carrier purge station is configured to receive a substrate carrier from one of the plurality of semiconductor processing tools, purge the substrate carrier with an inert gas, and determine if the substrate carrier needs repair. The carrier repair station is configured to receive a substrate carrier to be repaired and replace one or more parts in the substrate carrier.