Provided are a kit and a laminate which are capable of suppressing residues derived from a temporary adhesive in manufacture of a semiconductor. The kit for manufacturing a semiconductor device includes a composition which contains a solvent A; a composition which contains a solvent B; and a composition which contains a solvent C, in which the kit is used when a temporary adhesive layer is formed on a first substrate using a temporary adhesive composition containing a temporary adhesive and the solvent A, at least some of an excessive amount of the temporary adhesive on the first substrate is washed using the composition containing the solvent B, a laminate is manufactured by bonding the first substrate and a second substrate through the temporary adhesive layer, one of the first substrate and the second substrate is peeled off from the laminate at a temperature of lower than 40° C., and then the temporary adhesive remaining on at least one of the first substrate or the second substrate is washed using the composition containing the solvent C, and the solvent A, the solvent B, and the solvent C respectively satisfy a predetermined vapor pressure and a predetermined saturated solubility.

In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S—H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.

To manufacture an integrated circuit (IC) device, a structure in which a first material film including silicon atoms and nitrogen atoms and a second material film devoid of nitrogen atoms is formed on a substrate. A carbonyl compound having a functional group without an α-hydrogen is applied to the structure, and thus, an inhibitor is selectively formed only on an exposed surface of the first material film from among the first material film and the second material film.

Compounds for selectively forming metal-containing films are provided. Methods of forming metal-containing films are also provided. The methods include forming a blocking layer, for example, on a first substrate surface, by a first deposition process and forming the metal-containing film, for example, on a second substrate surface, by a second deposition process.

The present disclosure provides an adapter board for semiconductor device packaging and a method manufacturing the same. The method includes: providing a stacked structure including a support substrate, a separation layer, and a silicon substrate, a TSV is formed in the silicon substrate, the TSV is filled with a copper conductive pillar, a diffusion barrier is formed between the copper conductive pillar and a side walls of the TSV; grinding a top surface of the silicon substrate; polishing a top surface of the remaining silicon substrate using a chemical mechanical polishing process until the TSV is exposed; etching the copper conductive pillar to form a groove; filling the groove with a protective layer; etching the top surface of the silicon substrate to expose the copper conductive pillar; forming an insulating layer on the top surface of the silicon substrate using a chemical vapor deposition process.

Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.

A substrate processing method is provided. In the method, a substrate is provided. A monomer that is chemically bonded to the substrate is supplied onto the substrate. An initiator for polymerizing the monomer is supplied to the substrate having the supplied monomer thereon, thereby forming a polymer film.

A compound-semiconductor photovoltaic cell includes a first photoelectric conversion cell made of a first compound-semiconductor material which lattice matches with GaAs or Ge; a first tunnel junction layer arranged on a deep side farther than the first photoelectric conversion cell in a light incident direction, and including a first p-type (Al.sub.x1Ga.sub.1-x1).sub.y1In.sub.1-y1As (0≤x1<1, 0<y1≤1) layer and a first n-type (Al.sub.x2Ga.sub.1-x2).sub.y2In.sub.1-y2P (0≤x2<1, 0<y2<1) layer; and a second photoelectric conversion cell arranged on a deep side farther than the first tunnel junction layer in the light incident direction, and made of a second compound-semiconductor material which is a GaAs-based semiconductor material. The first photoelectric conversion cell and the second photoelectric conversion cell are joined via the first tunnel junction layer, and a lattice constant of the first n-type (Al.sub.x2Ga.sub.1-x2).sub.y2In.sub.1-y2P layer is greater than a lattice constant of the first photoelectric conversion cell.

What is provided is a transistor including a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode, in which the gate insulating film is a laminated film in which a SiO.sub.x film and a SiC.sub.yN.sub.z film are alternately formed, the total number of films constituting the laminated film is 3 or more and 18 or less, and the thickness of each film constituting the laminated film is 25 nm or more and 150 nm or less.