Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

In a method of manufacturing a semiconductor device, a first fin structure, a second fin structure, a first wall fin structure and a second wall fin structure are formed over a substrate. The first and second fin structures are disposed between the first and second wall fin structures, and lower portions of the first and second fin structures and the first and second wall fin structures are embedded in the isolation insulating layer and upper portions thereof are exposed from the isolation insulating layer. A sidewall spacer layer is formed on sidewalls of the first and second fin structures. Source/drain regions of the first and second fin structures are recessed. An epitaxial source/drain structure is formed over the recessed first and second fin structures. A width W1 of the first and second fin structures is smaller than a thickness W2 of the sidewall spacer layer.

A method of forming an integrated circuit that includes placing a semiconductor substrate in a process chamber at an initial temperature, wherein one or more trenches are located within the semiconductor substrate. The temperature of the substrate is increased in a substantially oxygen-free ambient to an oxide-growth temperature. The temperature is then maintained at the oxide growth temperature while providing an oxidizing ambient, thereby forming an oxide layer on sidewalls of the trench. The temperature of the semiconductor wafer is then reduced to a final temperature below the initial temperature and removed from the process chamber.

The present disclosure provides a high electron mobility transistor including a channel layer; a barrier layer on the channel layer and configured to induce formation of a 2-dimensional electron gas (2DEG) to the channel layer; a p-type semiconductor layer on the barrier layer; a first passivation layer on the barrier layer and including a quaternary material of Al, Ga, O, and N; a gate electrode on the p-type semiconductor layer; and a source electrode and a drain electrode provided on both sides of the barrier layer and separated from the gate electrode.

Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.

A plasma processing method includes: providing a substrate including: (a) an etching target film; (b) a photoresist film on an upper surface of the etching target film, having a side surface that defines at least one opening in the upper surface of the etching target film; and (c) a first film including a first portion on an upper surface of the photoresist film and second portion on the side surface of the photoresist film, the first portion having a film thickness larger than that of the second portion; and trimming at least a part of the side surface of the photoresist film and at least a part of the second portion of the first film.

Methods of improved selectively for SAM-based selective depositions are described. Some of the methods include forming a SAM on a second surface and a carbonized layer on the first surface. The substrate is exposed to an oxygenating agent to remove the carbonized layer from the first surface, and a film is deposited on the first surface over the protected second surface. Some of the methods include overdosing a SAM molecule to form a SAM layer and SAM agglomerates, depositing a film, removing the agglomerates, reforming the SAM layer and redepositing the film.

Methods and related systems for topographically depositing a material on a substrate are disclosed. The substrate comprises a proximal surface and a gap feature. The gap feature comprises a sidewall and a distal surface. Exemplary methods comprise, in the given order: a step of positioning the substrate on a substrate support in a reaction chamber; a step of subjecting the substrate to a plasma pre-treatment; and, a step of selectively depositing a material on at least one of the proximal surface and the distal surface with respect to the sidewall. The step of subjecting the substrate to a plasma pre-treatment comprises exposing the substrate to at least one of fluorine-containing molecules, ions, and radicals.

Processing methods disclosed herein comprise forming a nucleation layer and a flowable chemical vapor deposition (FCVD) film on a substrate surface by exposing the substrate surface to a silicon-containing precursor and a reactant. By controlling at least one of a precursor/reactant pressure ratio, a precursor/reactant flow ratio and substrate temperature formation of miniature defects is minimized. Controlling at least one of the process parameters may reduce the number of miniature defects. The FCVD film can be cured by any suitable curing process to form a smooth FCVD film.

An embodiment of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a base; and forming a silicon nitride film layer on the base by an atomic layer deposition process, where the atomic layer deposition process includes multiple cyclic deposition steps; in each of the cyclic deposition steps, a silicon source gas and a nitrogen source gas are provided to a surface of the base; before each of the cyclic deposition steps, the method of manufacturing a semiconductor structure further includes a repair step; in the repair step, a repair gas is provided to the surface of the base, and the repair gas is a hydrogen-containing repair gas; the repair gas includes a polar molecule for repairing the surface of the base that is damaged.