Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more recessed features along the substrate and a seam or void may be defined by the silicon-containing material within at least one of the one or more recessed features along the substrate. The methods may also include treating the silicon-containing material with a hydrogen-containing gas, such as plasma effluents of the hydrogen-containing gas, which may cause a size of the seam or void to be reduced.

The present disclosure describes a semiconductor device that includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The source/drain region includes (i) a first epitaxial structure embedded in the substrate; (ii) a nitride layer on the first epitaxial structure; and a second epitaxial structure on the first epitaxial structure. The semiconductor device also includes a gate structure formed on the nanostructures.

A semiconductor structure includes a first FinFET device disposed over a substrate, a second FinFET device disposed over the substrate, and an isolation structure. The first FinFET device includes at least a first fin and a first metal gate structure over the first fin. The second FinFET device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.

Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.

Exemplary semiconductor processing methods may include flowing deposition gases that may include a nitrogen-containing precursor, a silicon-containing precursor, and a carrier gas, into a substrate processing region of a substrate processing chamber. The flow rate ratio of the nitrogen-containing precursor to the silicon-containing precursor may be greater than or about 1:1. The methods may further include generating a deposition plasma from the deposition gases to form a silicon-and-nitrogen containing layer on a substrate in the substrate processing chamber. The silicon-and-nitrogen-containing layer may be treated with a treatment plasma, where the treatment plasma is formed from the carrier gas without the silicon-containing precursor. The flow rate of the carrier gas in the treatment plasma may be greater than a flow rate of the carrier gas in the deposition plasma.

Methods of and systems for reforming films comprising silicon nitride are disclosed. Exemplary methods include providing a substrate within a reaction chamber, forming activated species by irradiating a reforming gas with microwave radiation, and exposing substrate to the activated species. A pressure within the reaction chamber during the step of forming activated species can be less than 50 Pa.

Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

A semiconductor device with a small variation in characteristics is provided. A semiconductor device includes an oxide, a first conductor and a second conductor over the oxide, a first insulator over the first conductor, a second insulator over the second conductor, a third insulator over the first insulator and the second insulator, a fourth insulator over the third insulator, a fifth insulator that is over the oxide and placed between the first conductor and the second conductor, a sixth insulator over the fifth insulator, and a third conductor over the sixth insulator. The third conductor includes a region overlapping the oxide. The fifth insulator includes a region in contact with the oxide, the first conductor, the second conductor, and each of the first insulator to the fourth insulator. The fifth insulator contains nitrogen, oxygen, and silicon.

A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes a first insulator; a second insulator having an opening over the first insulator; a third insulator that has a first depressed portion and is provided inside the opening; a first oxide that has a second depressed portion and is provided inside the first depressed portion; a second oxide provided inside the second depressed portion; a first conductor and a second conductor that are electrically connected to the second oxide and are apart from each other; a fourth insulator over the second oxide; and a third conductor including a region overlapping with the second oxide with the fourth insulator therebetween. The second oxide includes a first region, a second region, and a third region sandwiched between the first region and the second region in a top view. The first conductor includes a region overlapping with the first region and the second insulator. The second conductor includes a region overlapping with the second region and the second insulator. The third conductor includes a region overlapping with the third region.