Disclosed is an epitaxial substrate with a 2D material interposer on a surface of a polycrystalline substrate. The ultra-thin 2D material interposer is grown by van der Waals epitaxy. The lattice constant of a surface layer of the ultra-thin 2D material interposer and the coefficient of thermal expansion of the substrate base are highly fit with those of AlGaN or GaN. The ultra-thin 2D material interposer is of a single-layer structure or a composite-layer structure. An AlGaN or GaN single crystalline epitaxial layer is grown on the ultra-thin 2D material interposer by virtue of the van der Waals epitaxy. Therefore, the large-size substrate may be manufactured with far lower costs than related single crystal wafers.

A method for growing a semiconductor material over a Si-based substrate includes providing the Si-based substrate; growing a monocrystalline refractory-metal ceramic film directly over the Si-based substrate; and depositing a semiconductor film directly over the monocrystalline refractory-metal ceramic film. The monocrystalline refractory-metal ceramic film has a thickness less than 300 nm.

There is provided a film forming method including: adsorbing fluorine onto a substrate on which a region in which a nitride film is exposed and a region in which an oxide film is exposed are provided adjacent to each other by supplying a fluorine-containing gas to the substrate, and forming a stepped surface on a side surface of the oxide film by selectively etching the nitride film, among the nitride film and the oxide film, so as to cause a surface of the nitride film to be more deeply recessed than a surface of the oxide film; and after the adsorbing the fluorine onto the substrate and forming the stepped surface, selectively forming a semiconductor film on the nitride film, among the nitride film and the oxide film, by supplying a raw material gas including a semiconductor material to the substrate.

This invention in one aspect relates to a method of synthesizing a self-assembled mixed-dimensional heterostructure including 2D metallic borophene and 1D semiconducting armchair-oriented graphene nanoribbons (aGNRs). The method includes depositing boron on a substrate to grow borophene thereon at a substrate temperature in an ultrahigh vacuum (UHV) chamber; sequentially depositing 4,4″-dibromo-p-terphenyl on the borophene grown substrate at room temperature in the UHV chamber to form a composite structure; and controlling multi-step on-surface coupling reactions of the composite structure to self-assemble a borophene/graphene nanoribbon mixed-dimensional heterostructure. The borophene/aGNR lateral heterointerfaces are structurally and electronically abrupt, thus demonstrating atomically well-defined metal-semiconductor heterojunctions.

Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

A method for manufacturing an epitaxial wafer by forming a single crystal silicon layer on a wafer containing a group IV element including silicon, the method including the steps of: removing a natural oxide film on a surface of the wafer containing the group IV element including silicon in an atmosphere containing hydrogen; forming an oxygen atomic layer by oxidizing the wafer after removing the natural oxide film; and forming a single crystal silicon by epitaxial growth on the surface of the wafer after forming the oxygen atomic layer, where a planar density of oxygen in the oxygen atomic layer is set to 4×10.sup.14 atoms/cm.sup.2 or less. A method for manufacturing an epitaxial wafer having an epitaxial layer of good-quality single crystal silicon while also allowing the introduction of an oxygen atomic layer in an epitaxial layer stably and simply.

A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

A method for manufacturing a semiconductor structure is provided. The method includes a III-V semiconductor device in a first region of a base substrate and a further device in a second region of the base substrate. The method includes: (a) obtaining a base substrate comprising the first region and the second region, different from the first region; (b) providing a buffer layer over a surface of the base substrate at least in the first region, wherein the buffer layer comprises at least one monolayer of a first two-dimensional layered crystal material; (c) forming, over the buffer layer in the first region, and not in the second region, a III-V semiconductor material; and (d) forming, in the second region, at least part of the further device. A semiconductor structure is also provided.

A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×10.sup.14 cm.sup.−3 and less than or equal to 5×10.sup.16 cm.sup.−3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.