H01L21/02557

METHOD OF MANUFACTURING MULTI-COMPONENT SEMICONDUCTOR NANOCRYSTAL, MULTI-COMPONENT SEMICONDUCTOR NANOCRYSTAL, AND QUANTUM DOT INCLUDING THE SAME
20230028670 · 2023-01-26 ·

Provided are a method of manufacturing a multi-component semiconductor nanocrystal, a multi-component semiconductor nanocrystal manufactured by the method, and a quantum dot including the same. The method includes irradiating microwaves to a semiconductor nanocrystal synthesis composition, and the semiconductor nanocrystal synthesis composition includes a precursor including a Group I element, a precursor including a Group II element, a precursor including a Group III element, a precursor including a Group V element, a precursor including a Group VI element, or any combination thereof.

Method of forming transition metal dichalcogenide thin film

A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element.

Passivated nanoparticles
11656231 · 2023-05-23 · ·

Passivated semiconductor nanoparticles and methods for the fabrication and use of passivated semiconductor nanoparticles is provided herein.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

A SEED LAYER, A HETEROSTRUCTURE COMPRISING THE SEED LAYER AND A METHOD OF FORMING A LAYER OF MATERIAL USING THE SEED LAYER

A seed layer for inducing nucleation to form a layer of material is described. In an embodiment, the seed layer comprising a layer of two-dimensional monolayer amorphous material having a disordered atomic structure adapted to create localised electronic states to form electric potential wells for bonding adatoms to a surface of the seed layer via van der Waals interaction to form the layer of material, wherein each of the electric potential wells has a potential energy larger in magnitude than surrounding thermal energy to capture adatoms on the surface of the seed layer. Embodiments in relation to a method for forming the seed layer, a heterostructure comprising the seed layer, a method for forming the heterostructure comprising the seed layer, a device comprising the heterostructure and a method of enhancing vdW interaction between adatoms and a surface of the seed layer are also described.

ALLOYED SEMICONDUCTOR NANOCRYSTALS
20230207723 · 2023-06-29 ·

The invention relates to methods for preparing 3-element semiconductor nanocrystals of the formula WYxZ(1-x), wherein W is a Group II element, Y and Z are different Group VI elements, and 0<X<1, comprising dissolving a Group II element, a first Group VI element, and a second Group VI element in a one or more solvents. The Group II, VI and VI elements are combined to provide a II:VI:VI SCN precursor solution, which is heated to a temperature sufficient to produce semiconductor nanocrystals of the formula WYxZ(1-x). The solvent used to dissolve the Group II element comprises octadecene and a fatty acid. The solvent used to dissolve the Group VI elements comprises octadecene. The invention also includes semiconductor nanocrystals prepared according to the disclosed methods, as well as methods of using the semiconductor nanocrystals.

METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING COMBINED SEMICONDUCTOR SUBSTRATE, COMBINED SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR-JOINED SUBSTRATE

A method for manufacturing a semiconductor substrate according to the present invention includes preparing a seed substrate containing a semiconductor material, forming an ion implanted layer at a certain depth from a front surface of a main surface of the seed substrate by implanting ions into the seed substrate, growing a semiconductor layer on the main surface of the seed substrate with a vapor-phase synthesis method, and separating a semiconductor substrate including the semiconductor layer and a part of the seed substrate by irradiating the front surface of the main surface of at least any of the semiconductor layer and the seed substrate with light.

Method of making quantum dots
09850593 · 2017-12-26 · ·

Quantum dots and methods of making quantum dots are provided.

INTEGRATED CIRCUIT DIE HAVING REDUCED DEFECT GROUP III-NITRIDE LAYER AND METHODS ASSOCIATED THEREWITH

Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.

Method for manufacturing CZTS based thin film having dual band gap slope, method for manufacturing CZTS based solar cell having dual band gap slope and CZTS based solar cell thereof

A method for manufacturing a CZTS based thin film having a dual band gap slope, comprising the steps of: forming a Cu.sub.2ZnSnS.sub.4 thin film layer; forming a Cu.sub.2ZnSn(S,Se).sub.4 thin film layer; and forming a Cu.sub.2ZnSnS.sub.4 thin film layer. A method for manufacturing a CZTS based solar cell having a dual band gap slope according to another aspect of the present invention comprises the steps of: forming a back contact; and forming a CZTS based thin film layer on the back contact by the method described above.