Patent classifications
H01L21/02568
METHOD OF INCREASING SENSITIVITY AND LIMITS OF DETECTION AND CONTROLLING FLUID FLOW OVER SENSOR AND SENSOR ARRAY
A process of making sensors and sensor arrays that has the ability to manipulate of the morphology or flow of an applied drop or sample over the sensor array surface at any point in the patterning process and sensors and sensor arrays having increased sensitivity and limits of detection. In addition, said process can provided real time notification of any centerline deviation. Such production process can be adjusted in real time. Thus, large numbers of units can be made—even in millions of per day—with few if any out of specification units being produced. Such process does not require large-scale clean rooms and is easily configurable.
Field effect transistor using transition metal dichalcogenide and a method for forming the same
In a method of forming a two-dimensional material layer, a nucleation pattern is formed over a substrate, and a transition metal dichalcogenide (TMD) layer is formed such that the TMD layer laterally grows from the nucleation pattern. In one or more of the foregoing and following embodiments, the TMD layer is single crystalline.
Metal chalcogenide film and method and device for manufacturing the same
Provided are a metal chalcogenide thin film and a method and device for manufacturing the same. The metal chalcogenide thin film includes a transition metal element and a chalcogen element, and at least one of the transition metal element and the chalcogen element having a composition gradient along the surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient. The metal chalcogenide thin film may be prepared by using a manufacturing method including providing a transition metal precursor and a chalcogen precursor on a substrate by using a confined reaction space in such a manner that at least one of the transition metal precursor and the chalcogen precursor forms a concentration gradient according to a position on the surface of the substrate; and heat-treating the substrate.
System and method for making quantum dots
Embodiments of the present disclosure provide for methods of making quantum dots (QDs) (passivated or unpassivated) using a continuous flow process, systems for making QDs using a continuous flow process, and the like. In one or more embodiments, the QDs produced using embodiments of the present disclosure can be used in solar photovoltaic cells, bio-imaging, IR emitters, or LEDs.
FILM DEPOSITION METHOD AND ELEMENT INCLUDING FILM DEPOSITED BY THE FILM DEPOSITION METHOD
A film deposition method may include preparing a non-planar substrate including a first surface, a second surface, and an inclined surface between the first surface and the second surface; depositing a film having a thickness deviation on the first surface, the second surface, and the inclined surface; and etching the film deposited on the first surface, the second surface, and the inclined surface. A height of the second surface may be different than a height of the first surface.
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
A semiconductor device includes a substrate, a 2-D material layer, source/drain contacts, and a gate electrode. The 2-D material layer is over the substrate, the 2-D material layer includes source/drain regions and a channel region between the source/drain regions, in which the 2-D material layer is made of a transition metal dichalcogenide (TMD). The source/drain contacts are in contact with source/drain regions of the 2-D material layer, in which a binding energy of transition metal atoms at the channel region of the 2-D material layer is different from a binding energy of the transition metal atoms at the source/drain regions of the 2-D material layer. The gate electrode is over the substrate.
METHOD OF FORMING GERMANIUM ANTIMONY TELLURIUM FILM
A method of forming a germanium antimony tellurium (GeSbTe) layer includes forming a germanium antimony (GeSb) layer by repeatedly performing a GeSb supercycle; and forming the GeSbTe layer by performing a tellurization operation on the GeSb layer, wherein the GeSb supercycle includes performing at least one GeSb cycle; and performing at least one Sb cycle, the GeSbTe has a composition of Ge.sub.2Sb.sub.2+aTe.sub.5+b, in which a and b satisfy the following relations: −0.2<a<0.2 and −0.5<b<0.5.
SYNTHESIS AND USE OF PRECURSORS FOR ALD OF MOLYBDENUM OR TUNGSTEN CONTAINING THIN FILMS
Processes for forming Mo and W containing thin films, such as MoS.sub.2, WS.sub.2, MoSe.sub.2, and WSe.sub.2 thin films are provided. Methods are also provided for synthesizing Mo or W beta-diketonate precursors. Additionally, methods are provided for forming 2D materials containing Mo or W.
In situ monitoring of field-effect transistors during atomic layer deposition
A system and method for performing in-situ measurements of semiconductor devices during chemical vapor deposition (CVD) includes disposing a chip carrier within a sealed chamber of a reactor for carrying out in-situ monitoring of partially fabricated semiconductor devices. The chip carrier includes a plurality of metallized bonding pads disposed along both peripheral edges on a same surface of the base for making electrical connections to metallized pads or contacts on the semiconductor device through bonding wires. Each of the plurality of metallized bonding pads disposed along both peripheral edges is electrically connected to each other as a pair through electrically connecting to a corresponding pair of ports which are disposed along both peripheral edges of the chip carrier. In-situ monitoring of the partially fabricated semiconductor device is performed through connecting the plurality of ports on the chip carrier to an external source-measure unit through a connector and wire harness.
TWO-DIMENSIONAL SEMICONDUCTOR TRANSISTOR HAVING REDUCED HYSTERESIS AND MANUFACTURING METHOD THEREFOR
A two-dimensional semiconductor transistor includes a gate electrode, a gate insulating layer disposed on the gate electrode, an organic dopant layer disposed on the gate insulating layer and comprising an organic material including electrons, a two-dimensional semiconductor layer disposed on the organic dopant layer, a source electrode disposed on the two-dimensional semiconductor layer, and a drain electrode disposed on the two-dimensional semiconductor layer and spaced apart from the source electrode. A hysteresis of the two-dimensional semiconductor transistor is reduced due to the two-dimensional semiconductor transistor including the organic dopant layer.