Disclosed is a preparation method for a semiconductor structure. The semiconductor structure includes: a substrate; an epitaxial layer and an epitaxial structure that are stacked on the substrate in sequence. The epitaxial layer is doped with a doping element. In the forming process, a sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that a concentration of the doping element in the epitaxial layer is lower than a preset value. In this application, the sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that the concentration of the doping element in the epitaxial layer is lower than the preset value, so as to prevent the doping element in the epitaxial layer from being precipitated upward into an upper-layer structure, ensure the mobility of electrons in a channel layer, and improve the performance of a device.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and the concentration of boron in the center of the epitaxial layer is less than 5.0×10.sup.12 cm.sup.−3.

A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and the concentration of boron is less than 1.0×10.sup.14 cm.sup.−3 at any position in the plane of the epitaxial layer.

The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The source/drain region includes epitaxial end caps, where each epitaxial end cap is formed at an end portion of a nanostructure of the nanostructures. The source/drain region also includes an epitaxial body in contact with the epitaxial end caps and an epitaxial top cap formed on the epitaxial body. The semiconductor device further includes gate structure formed on the nanostructures.

A semiconductor laminate includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, and an epitaxial layer composed of silicon carbide disposed on the first main surface. The second main surface has an average value of roughness Ra of 0.1 μm or more and 1 μm or less with a standard deviation of 25% or less of the average value.

A method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a silicon carbide voltage-blocking-layer, the method includes: epitaxially growing a buffer layer on the substrate, doping a main dopant for determining a conductivity type of the buffer layer and doping an auxiliary dopant for capturing minority carriers in the buffer layer at a doping concentration less than the doping concentration of the main dopant, so that the buffer layer enhances capturing and extinction of the minority carriers, the minority carriers flowing in a direction from the voltage-blocking-layer to the substrate, so that the buffer layer has a lower resistivity than the voltage-blocking-layer, and so that the buffer layer includes silicon carbide as a main component; and epitaxially growing the voltage-blocking-layer on the buffer layer.

A method of removing a substrate from III-nitride based semiconductor layers with a cleaving technique. A growth restrict mask is formed on or above a substrate, and one or more III-nitride based semiconductor layers are grown on or above the substrate using the growth restrict mask. The III-nitride based semiconductor layers are bonded to a support substrate or film, and the III-nitride based semiconductor layers are removed from the substrate using a cleaving technique on a surface of the substrate. Stress may be applied to the III-nitride based semiconductor layers, due to differences in thermal expansion between the III-nitride substrate and the support substrate or film bonded to the III-nitride based semiconductor layers, before the III-nitride based semiconductor layers are removed from the substrate. Once removed, the substrate can be recycled, resulting in cost savings for device fabrication.

A silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.

A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes a first insulator; a second insulator having an opening over the first insulator; a third insulator that has a first depressed portion and is provided inside the opening; a first oxide that has a second depressed portion and is provided inside the first depressed portion; a second oxide provided inside the second depressed portion; a first conductor and a second conductor that are electrically connected to the second oxide and are apart from each other; a fourth insulator over the second oxide; and a third conductor including a region overlapping with the second oxide with the fourth insulator therebetween. The second oxide includes a first region, a second region, and a third region sandwiched between the first region and the second region in a top view. The first conductor includes a region overlapping with the first region and the second insulator. The second conductor includes a region overlapping with the second region and the second insulator. The third conductor includes a region overlapping with the third region.