Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.

A wafer processing apparatus is configured to process a wafer by supplying mist to a surface of the wafer. The wafer processing apparatus includes a furnace in which the wafer is disposed, a gas supplying device configured to supply gas into the furnace, a mist supplying device configured to supply the mist into the furnace, and a controller. The controller is configured to execute a processing step by controlling the gas supplying device and the mist supplying device to supply the gas and the mist into the furnace, respectively. The controller is further configured to control the mist supplying device to stop supplying the mist into the furnace while controlling the gas supplying device to keep supplying the gas into the furnace when the processing step ends.

A method for bonding detection includes: disposing a liquid crystal component on one side of a growth substrate away from a light-emitting element; disposing a first electrode layer on one side of the liquid crystal component away from the growth substrate, and disposing a first polarizer on one side of the first electrode layer away from the liquid crystal component; disposing a second electrode layer on one side of a transient substrate away from an adhesive layer, and disposing a second polarizer on one side of the second electrode layer away from the transient substrate, polarization directions of the second polarizer and the first polarizer are orthogonal; irradiating the first polarizer with a uniform light; electrifying the first electrode layer and the second electrode layer; and detecting a uniformity and a thickness of the adhesive layer according to the light exited from one side of the second polarizer.

A substrate treating method for treating substrates with a substrate treating apparatus having an indexer section, a treating section and an interface section includes performing resist film forming treatment in parallel on a plurality of stories provided in the treating section and performing developing treatment in parallel on a plurality of stories provided in the treating section.

Example embodiments may provide methods for determining a quality of a film in spin coating process. The methods may include capturing images of portions of the film using an imaging device while coating the film on a substrate using a spinner. The imaging device may include SPCs and lens and/or SLMs. The methods may also include determining whether a characteristic of the film matches to a standard based on the images of the portions of the film. The method may further include performing detecting that the quality of the film is optimal in response to determining that the characteristic of the film matches to the standard or detecting that the quality of the film is not optimal in response to determining that the characteristic of the film does not match to the standard.

A vertical field effect transistor according to an embodiment of the present invention does not require a spacer and, accordingly, remarkably alleviates the problem that electric charge is scattered at an interface, thereby having excellent electrical characteristics. The vertical field effect transistor includes a substrate, a source electrode positioned on the substrate, an active layer positioned on the source electrode and having vertically grown crystal grains, a drain electrode positioned on the active layer to be spaced by the active layer away from the source electrode, a gate insulating layer positioned on a lateral surface of the active layer, and a gate electrode positioned on the gate insulating layer.

A low-cost separation method with high mass productivity is provided. A first layer with a thickness of 0.1 μm or more and 3 μm or less can be formed by using a photosensitive and thermosetting material over the formation substrate, a resin layer comprising an opening is formed by forming an opening in the first layer by using a photolithography method, a silicon layer or an oxide layer is formed so as to overlap with the opening of the resin layer, a transistor including a metal oxide is formed over the resin layer, a conductive layer formed in the same manufacturing steps as the source or drain of the transistor is formed over the silicon layer or the oxide layer, the resin layer and one of the silicon layer and the oxide layer are irradiated with the laser light, and the transistor and the conductive layer are separated from the formation substrate.

Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed.

The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.

A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies.