H01L21/02661

LIFT PIN, WAFER PROCESSING APPARATUS COMPRISING SAME, AND METHOD FOR PRODUCING WAFERS
20230039939 · 2023-02-09 ·

One embodiment provides a lift pin comprising: a body which is inserted into a through-hole in a susceptor; and a head provided at the end of the body to come into contact with the underside of a wafer, wherein the top surface of the head is formed to have a concavoconvex structure.

Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation
11557474 · 2023-01-17 · ·

A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

Method for manufacturing display apparatus

A manufacturing method of a display apparatus including preparing a substrate, forming an amorphous silicon layer on the substrate, cleaning the amorphous silicon layer with hydrofluoric acid, crystallizing the amorphous silicon layer into a polycrystalline silicon layer, and forming a metal layer directly on the polycrystalline silicon layer.

Semiconductor device and forming method thereof

A semiconductor device includes a semiconductor substrate, a semiconductor fin extending from the semiconductor substrate, a gate structure extending across the semiconductor fin, and source/drain semiconductor layers on opposite sides of the gate structure. The source/drain semiconductor layers each have a first thickness over a top side of the semiconductor fin and a second thickness over a lateral side of the semiconductor fin. The first thickness and the second thickness have a difference smaller than about 20 percent of the first thickness.

Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof

A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.

METHOD AND WAFER PROCESSING FURNACE FOR FORMING AN EPITAXIAL STACK OF SEMICONDUCTOR EPITAXIAL LAYERS

A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing plurality of substrates to a process chamber. A plurality of deposition cycles are executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial comprises a plurality of epitaxial pairs, each pair comprising a first epitaxial layer and a second epitaxial layer. The deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer and the second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer

Light emitting display device and manufacturing method thereof

A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 μm to about 2 μm, and a length of the channel of the third transistor is in a range of about 1 μm to about 2.5 μm.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

INTEGRATED EPITAXY AND PRECLEAN SYSTEM

Embodiments of the present disclosure generally relate to an integrated substrate processing system for cleaning a substrate surface and subsequently performing an epitaxial deposition process thereon. A processing system includes a film formation chamber, a transfer chamber coupled to the film formation chamber, and an oxide removal chamber coupled to the transfer chamber, the oxide removal chamber having a substrate support. The processing system includes a controller configured to introduce a process gas mixture into the oxide removal chamber, the process gas mixture including a fluorine-containing gas and a vapor including at least one of water, an alcohol, an organic acid, or combinations thereof. The controller is configured to expose a substrate positioned on the substrate support to the process gas mixture, thereby removing an oxide film from the substrate.

Semiconductor device structure and methods of its production
RE049285 · 2022-11-08 · ·

The present document discloses a semiconductor device structure (1) comprising a SiC substrate (11), an In.sub.x1Al.sub.y1Ga.sub.1-x1-y1N buffer layer (13), wherein x1=0-1, y1=0-1 and x1+y1=1, and an In.sub.x2Al.sub.y2Ga.sub.1-x2-y2N nucleation layer (12), wherein x2=0-1, y2=0-1 and x2+y2=1, sandwiched between the SiC substrate (11) and the buffer layer (13). The buffer layer (13) presents a rocking curve with a (102) peak having a FWHM below 250 arcsec, and the nucleation layer (12) presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD). Methods of making such a semiconductor device structure are disclosed.