A film forming method includes: forming a laminated film, in which an interface layer, a bulk layer, and a surface layer are laminated in this order, on a base; and crystallizing the laminated film, wherein the bulk layer is formed of a film that is easier to crystallize than the interface layer in crystallizing the laminated film, and wherein the surface layer is formed of a film that is easier to crystallize than the bulk layer in crystallizing the laminated film.

A semiconductor device includes a substrate and a semiconductor layer. The substrate includes a planar portion and a plurality of pillars on a periphery of the planar portion. The pillars are shaped as rectangular columns, and corners of two of the pillars at the same side of the planar portion are aligned in a horizontal direction or a direction perpendicular to the horizontal direction. The semiconductor layer is disposed over the planar portion and between the pillars.

A semiconductor device include a substrate, a buffer layer formed on the substrate, a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer, polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer, a source electrode and a drain electrode formed on the polycrystalline source and the drain, a gate electrode corresponding to the channel layer, and an NiSi.sub.2 contact layer located between the source and the source electrode and between the drain and the drain electrode.

In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.

Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.

Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.

A method of manufacturing a semiconductor device includes steps of (i) forming a buffer layer of an insulating material on a substrate, (ii) forming a seed layer of catalyst material containing Ni on the buffer layer, (iii) forming, on the buffer layer, an amorphous intrinsic silicon layer for forming a channel, (iv) forming, on the amorphous intrinsic silicon layer, a non-intrinsic silicon layer for forming a source and/or drain, (v) forming a metal layer on the non-intrinsic silicon layer, and (vi) performing metal induced crystallization (MIC) process for crystallization of the amorphous intrinsic silicon layer and the amorphous non-intrinsic silicon layer, and activation of the amorphous non-intrinsic silicon layer to form a conductive area.

According to an embodiment, a semiconductor manufacturing method includes forming a first seed layer on an underlying layer with a first gas that is an aminosilane gas. The method further includes forming a first amorphous silicon layer on the first seed layer with a second gas that is a silane gas not containing an amino group. The method further includes forming a second seed layer containing impurities on the first amorphous silicon layer with a third gas that is an aminosilane gas. The method further includes forming a second amorphous silicon layer on the second seed layer with a fourth gas that is a silane gas not containing an amino group.

A semiconductor device include a substrate, a buffer layer formed on the substrate, a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer, polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer, a source electrode and a drain electrode formed on the polycrystalline source and the drain, a gate electrode corresponding to the channel layer, and an NiSi.sub.2 contact layer located between the source and the source electrode and between the drain and the drain electrode.

A method of manufacturing a semiconductor device includes steps of (i) forming a buffer layer of an insulating material on a substrate, (ii) forming a seed layer of catalyst material containing Ni on the buffer layer, (iii) forming, on the buffer layer, an amorphous intrinsic silicon layer for forming a channel, (iv) forming, on the amorphous intrinsic silicon layer, a non-intrinsic silicon layer for forming a source and/or drain, (v) forming a metal layer on the non-intrinsic silicon layer, and (vi) performing metal induced crystallization (MIC) process for crystallization of the amorphous intrinsic silicon layer and the amorphous non-intrinsic silicon layer, and activation of the amorphous non-intrinsic silicon layer to form a conductive area.