The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

The present invention provides a display panel, a fabricating method thereof and a display device. The display panel comprises a pixel region and a fan-out region, first signal lines and second signal lines are provided to intersect each other in the pixel region, and extend into the fan-out region, respectively, a first insulation layer is provided between the first signal lines and the second signal lines, a second insulation layer is provided on the second signal lines, the second insulation layer comprises at least four layers of structures, and a density of each layer of structure of the second insulation layer decreases gradually along a direction away from the first insulation layer. A size of the via hole formed in the second insulation layer by etching is smaller than that of the via hole formed in the prior art.

A liquid crystal display includes a first substrate, a gate line and a data line disposed on the first substrate, a first thin film transistor and a second thin film transistor connected to the gate line and the data line, a first subpixel electrode connected to the first thin film transistor, a resistor connected to the second thin film transistor and a resistance of the resistor is changed by a pulsed gate-on signal applied to the gate line, and a second subpixel electrode connected to the resistor.

The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).

Methods and systems are presented for heterogeneous integration of photonics and electronics with atomic layer deposition (ALD) bonding. One method includes operations for forming a compound semiconductor and for depositing (e.g., via atomic layer deposition) a continuous film of a protection material (e.g., Al.sub.2O.sub.3) on a first surface of the compound semiconductor. Further, the method includes an operation for forming a silicon on insulator (SOI) wafer, with the SOI wafer comprising one or more waveguides. The method further includes bonding the compound semiconductor at the first surface to the SOI wafer to form a bonded structure and processing the bonded structure. The protection material protects the compound semiconductor from acid etchants during further processing of the bonded structure.

Semiconductor devices are provided. A semiconductor device includes a first portion of a lower electrode structure on a substrate. The semiconductor device includes a first support pattern being in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device includes a second portion of the lower electrode structure on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device includes an upper electrode on the second portion of the lower electrode structure and on the first support pattern. Moreover, the semiconductor device includes a dielectric layer between the upper electrode and the second portion of the lower electrode structure.

Semiconductor devices are provided. A semiconductor device includes a first portion of a lower electrode structure on a substrate. The semiconductor device includes a first support pattern being in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device includes a second portion of the lower electrode structure on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device includes an upper electrode on the second portion of the lower electrode structure and on the first support pattern. Moreover, the semiconductor device includes a dielectric layer between the upper electrode and the second portion of the lower electrode structure.

Semiconductor devices are provided. A semiconductor device includes a first portion of a lower electrode structure on a substrate. The semiconductor device includes a first support pattern being in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device includes a second portion of the lower electrode structure on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device includes an upper electrode on the second portion of the lower electrode structure and on the first support pattern. Moreover, the semiconductor device includes a dielectric layer between the upper electrode and the second portion of the lower electrode structure.

Semiconductor devices are provided. A semiconductor device includes a first portion of a lower electrode structure on a substrate. The semiconductor device includes a first support pattern being in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device includes a second portion of the lower electrode structure on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device includes an upper electrode on the second portion of the lower electrode structure and on the first support pattern. Moreover, the semiconductor device includes a dielectric layer between the upper electrode and the second portion of the lower electrode structure.

The disclosure provides a method of manufacturing a display panel, including: sequentially forming a buffer layer, an oxide semiconductor layer, and a photoresist layer on a substrate; removing the photoresist layer corresponding to a gate defining region to obtain a photoresist section; forming a first metal layer on the photoresist layer and the oxide semiconductor layer which is not covered by the photoresist layer; and peeling off the photoresist section to remove the first metal layer on the photoresist section, wherein the first metal layer which corresponds to the gate defining region remains to obtain a gate.