An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. The gate includes noble metal nanoparticles. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region.

According to one embodiment, an isolator includes first and second conductive members, and first second, and third insulating members. The first conductive member includes first, second, and third partial regions. The third partial region is between the first and second partial regions. The second conductive member is electrically connected to the first conductive member. The second conductive member includes fourth and fifth partial regions. The fourth partial region is between the third and fifth partial regions. The first insulating member includes first and second insulating regions. The fifth partial region is between the first and second insulating regions. The second insulating member includes third and fourth insulating regions. The fourth partial region is between the third and fourth insulating regions. The third insulating member includes first and second portions.

A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device further includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size smaller than the first grain size.

A semiconductor device including a substrate including a recess; a gate insulation layer on a surface of the recess; a first gate pattern on the gate insulation layer and filling a lower portion of the recess; a second gate pattern on the first gate pattern in the recess and including a material having a work function different from a work function of the first gate pattern; a capping insulation pattern on the second gate pattern and filling an upper portion of the recess; a leakage blocking oxide layer on the gate insulation layer at an upper sidewall of the recess above an upper surface of the first gate pattern and contacting a sidewall of the capping insulation pattern; and impurity regions in the substrate and adjacent to the upper sidewall of the recess, each impurity region having a lower surface higher than the upper surface of the first gate pattern.

A method for manufacturing a semiconductor device (10) includes, in the following order: forming a first insulating film (14) on a semiconductor substrate (12); forming, on the first insulating film (14), wiring in which at least the uppermost layer is made of Au (16); implanting ions, which do not impair insulating properties even when implanted into the insulating film (14), into the upper surface of the wiring (16) and a region not covered with the wiring (16) on the upper surface of the first insulating film (14); and forming a second insulating film (18) that covers the wiring (16).

A semiconductor device including a substrate including a recess; a gate insulation layer on a surface of the recess; a first gate pattern on the gate insulation layer and filling a lower portion of the recess; a second gate pattern on the first gate pattern in the recess and including a material having a work function different from a work function of the first gate pattern; a capping insulation pattern on the second gate pattern and filling an upper portion of the recess; a leakage blocking oxide layer on the gate insulation layer at an upper sidewall of the recess above an upper surface of the first gate pattern and contacting a sidewall of the capping insulation pattern; and impurity regions in the substrate and adjacent to the upper sidewall of the recess, each impurity region having a lower surface higher than the upper surface of the first gate pattern.

A method for manufacturing a semiconductor device (10) includes, in the following order: forming a first insulating film (14) on a semiconductor substrate (12); forming, on the first insulating film (14), wiring in which at least the uppermost layer is made of Au (16); implanting ions, which do not impair insulating properties even when implanted into the insulating film (14), into the upper surface of the wiring (16) and a region not covered with the wiring (16) on the upper surface of the first insulating film (14); and forming a second insulating film (18) that covers the wiring (16).

A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device further includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size smaller than the first grain size.

A semiconductor device includes a first polysilicon structure, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size different from the first grain size.

A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; sequentially forming stacked layers of a gate oxide layer and a gate polysilicon layer on the semiconductor substrate; performing fluorine ion implantation at a predetermined temperature after forming the gate polysilicon layer, and annealing after the ion implantation to form Si—F bonds at an interface between the gate oxide layer and the semiconductor substrate; in which the predetermined temperature is between −100° C. and −10° C.