Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

A method for manufacturing a semiconductor device comprising: providing a substrate, wherein a first gate structure corresponding to a dense area transistor and a second gate structure corresponding to an isolated area transistor are formed on the substrate, and the first gate structure is higher than the second gate structure; forming a buffer layer over the second gate structure, wherein the upper surface of the buffer layer is flush with the upper surface of the first gate structure; and removing the top of the first gate structure, and forming a hard mask filling layer on a top area of the first gate structure.

In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.

A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.

The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.

The on-resistance of each of field effect transistors having different planar sizes is reduced. A semiconductor device includes first and second field effect transistors mounted on a semiconductor substrate and an insulating layer provided on a main surface of the semiconductor substrate. Here, each of the first and second field effect transistors includes a pair of main electrodes which are separated from each other and provided on the main surface of the semiconductor substrate, a cavity part which is provided in the insulating layer between the pair of main electrodes, and a gate electrode which has a head part positioned on the insulating layer and a body part that penetrates the insulating layer from the head part and protrudes toward the cavity part and in which the head part is wider than the body part. Here, the width of the cavity part of the second field effect transistor is different from the width of the cavity part of the first field effect transistor.

A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

A semiconductor device includes a channel layer, a barrier layer, and at least one contact layer. The channel layer includes a GaN-based material. The barrier layer includes an AlInN-based material in which a composition ratio of In is higher than 18%, and is provided on the channel layer. The at least one contact layer includes a conductive-type semiconductor material and is provided to penetrate the barrier layer and reach the channel layer.

Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.