A semiconductor device includes: a semiconductor layer having a first main surface in which a region for a first element is formed; and an element isolation portion configured to partition a first active region in the region for the first element. The first element includes: a first gate electrode, a first gate insulating film, a first-conduction-type first source region and a first-conduction-type first drain region, a first-conduction-type first source extension portion and a first-conduction-type first drain extension portion, and a second-conduction-type second source extension portion and a second-conduction-type second drain extension portion.

A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x≦0.2, and having a pH less than or equal to 1.5.

A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.

A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.

Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.

Processing methods may be performed to form an airgap in a semiconductor structure. The methods may include forming a high-k material on a floor of a trench. The trench may be defined on a semiconductor substrate between sidewalls of a first material and a spacer material. The methods may include forming a gate structure on the high-k material. The gate structure may contact the first material along each sidewall of the trench. The methods may also include etching the first material. The etching may form an airgap adjacent the gate structure.

An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.