A method for manufacturing a semiconductor device of an embodiment includes: forming a first film on a semiconductor layer containing silicon (Si), the first film containing a metal element and oxygen (O) and having a first thickness; and forming a second film between the semiconductor layer and the first film using radical oxidation, the second film containing silicon (Si) and oxygen (O) and having a second thickness larger than the first thickness.

A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

A semiconductor structure and a method for forming a semiconductor structure are provided. In some embodiments, a method is provided. The method includes following operations. A sacrificial gate structure is formed over a fin structure. The sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer. The sacrificial gate layer is removed to form a gate trench exposing the sacrificial dielectric layer. A doped region is formed in the fi structure covered by the sacrificial dielectric layer. The sacrificial dielectric layer, a portion of the doped region and a portion of the fin structure are removed from the gate trench. An interfacial layer is formed over the fin structure in the gate trench.

A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×10.sup.14 atoms/cm.sup.3 and/or germanium at a concentration of at least about 1×10.sup.19 atoms/cm.sup.3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

The present disclosure relates to the technical field of semiconductors and discloses a semiconductor device and a manufacturing method therefor. Forms of the method may include: providing a substrate structure, where the substrate structure includes: a semiconductor substrate, a semiconductor fin on the semiconductor substrate, isolation regions at two sides of the semiconductor fin, a gate dielectric layer on a surface of the semiconductor fin above the isolation regions, and a gate on a part of the gate dielectric layer; and performing threshold voltage adjustment ion implantation on a part of the semiconductor fin that is not covered by the gate, so as to enable implanted impurities to diffuse into a part of the semiconductor fin that is covered by the gate. Forms of the present disclosure can reduce loss of impurities implanted by the threshold voltage adjustment ion implantation.

A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×10.sup.14 atoms/cm.sup.3 and/or germanium at a concentration of at least about 1×10.sup.19 atoms/cm.sup.3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.

The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å.

A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H.sub.2O.sub.2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.