A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.

Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.

There is provided a semiconductor element containing gallium nitride. The semiconductor element includes a semiconductor layer including a first surface having a first region and a second region that is a projecting portion having a strip shape and projecting relative to the first region or a recessed portion having a strip shape and being recessed relative to the first region. Of the first surface, at least one of surfaces of the first region and the second region includes a crystal plane having a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation.

A semiconductor device includes a channel layer, a barrier layer, and at least one contact layer. The channel layer includes a GaN-based material. The barrier layer includes an AlInN-based material in which a composition ratio of In is higher than 18%, and is provided on the channel layer. The at least one contact layer includes a conductive-type semiconductor material and is provided to penetrate the barrier layer and reach the channel layer.

A GaN-based compound semiconductor device includes a GaN-based epitaxial structure and an annealed metal layered structure that is formed on the GaN-based epitaxial structure. The annealed metal layered structure includes a metallic barrier layer, a conductive unit, and a protective unit which is formed on a lateral surface of the conductive unit. The metallic barrier layer and the conductive unit are sequentially disposed on the GaN-based epitaxial structure in such order. An ohmic contact is formed between the GaN-based epitaxial structure and the annealed metal layered structure. The protective unit includes a metal oxide material having one of NiAlO, AuAlO, and a combination thereof.

A semiconductor device and fabricating method thereof is disclosed. The method comprises depositing epitaxial layers over a silicon substrate to form a semiconductor layer surface; forming at least one mesa portion on the semiconductor layer surface; depositing a metal stack on the semiconductor layer surface; subjecting the semiconductor layer surface to a rapid thermal annealing system for a two-step ohmic contact annealing in H.sub.2/N.sub.2 forming gas (FG) and then nitrogen; subjecting the semiconductor layer surface to an oxygen plasma treatment; and depositing a T-shaped metal gate on the semiconductor layer surface. A semiconductor device comprises a semiconductor layer surface having an epitaxial layer disposed over a silicon substrate; at least one mesa portion formed on the semiconductor layer surface; a metal stack, disposed on the semiconductor layer surface, and sequentially annealed in FG and nitrogen; and a T-shaped metal gate on the semiconductor layer surface.

III-Nitride heterostructures with low p-type sheet resistance and III-Nitride heterostructure devices with gate recess and devices including the III-Nitride heterostructures are disclosed.

An electrostatically controlled sensor includes a GaN/AlGaN heterostructure having a 2DEG channel in the GaN layer. Source and drain contacts are electrically coupled to the 2DEG channel through the AlGaN layer. A gate dielectric is formed over the AlGaN layer, and gate electrodes are formed over the gate dielectric, wherein each gate electrode extends substantially entirely between the source and drain contacts, wherein the gate electrodes are separated by one or more gaps (which also extend substantially entirely between the source and drain contacts). Each of the one or more gaps defines a corresponding sensing area between the gate electrodes for receiving an external influence. A bias voltage is applied to the gate electrodes, such that regions of the 2DEG channel below the gate electrodes are completely depleted, and regions of the 2DEG channel below the one or more gaps in the direction from source to drain are partially depleted.