A semiconductor device and a process of forming the semiconductor device are disclosed. The semiconductor device type of a high electron mobility transistor (HEMT) has double SiN films on a semiconductor layer, where the first SiN film is formed by the lower pressure chemical vapor deposition (LPCVD) technique, while, the second SiN film is deposited by the plasma assisted CVD (p-CVD) technique. Moreover, the gate electrode has an arrangement of double metals, one of which contains nickel (Ni) as a Schottky metal, while the other is free from Ni and covers the former metal. A feature of the invention is that the first metal is in contact with the semiconductor layer but apart from the second SiN film.

The present disclosure relates to a high electron mobility transistor (HEMT) and a fabrication method thereof. The HEMT may include a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a semiconductor gate disposed on the barrier layer; a metal gate disposed on the semiconductor gate, the metal gate having a trapezoidal cross-sectional shape; and a passivation layer directly contacting the metal gate. A first surface of the metal gate contacts a first surface of the semiconductor gate, and an edge of the first surface of the metal gate is located inside an edge of the first surface of the semiconductor gate.

A low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation and a preparation method thereof. The low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation provided by the present disclosure includes a substrate layer, a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer, which are arranged in sequence from bottom to top; a cathode arranged on the AlGaN barrier layer; a groove arranged in the GaN channel layer and the AlGaN barrier layer, and an anode provided on a bottom and a side wall of the groove and part of the AlGaN barrier layer; a dielectric layer provided on an uncovered portion of the AlGaN barrier layer; wherein, a contact portion of the anode with the groove and the AlGaN barrier layer is W or Mo metal with a crystal orientation of <100>.

A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.

A junction barrier Schottky diode device and a method for fabricating the same is disclosed. In the junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.

The present invention provides a GaN/two-dimensional AlN heterojunction rectifier on a silicon substrate and a preparation method therefor and belongs to the field of rectifiers. The rectifier comprises a silicon substrate, a GaN buffer layer, a carbon-doped semi-insulating GaN layer, a two-dimensional AlN layer, a non-doped GaN layer, a non-doped InGaN layer and a SiN.sub.x passivation layer that are stacked in sequence. The rectifier further comprises a mesa isolation groove and a Schottky contact electrode that are arranged at one side. The mesa isolation groove is in contact with the non-doped GaN layer, the non-doped InGaN layer, the SiN.sub.x passivation layer and the Schottky contact electrode. The Schottky contact electrode is in contact with the mesa isolation groove and the non-doped GaN layer. The thickness of the two-dimensional AlN layer is only several atomic layers, thus the received stress and polarization intensity are greater than those of the AlGaN layer.

A method of manufacturing a semiconductor device including a substrate; a first nitride layer containing gallium on the substrate; and a second nitride layer containing silicon on the first nitride layer includes generating an etchant of a gas containing chlorine atoms or bromine atoms; and selectively removing the second nitride layer, wherein the etchant is generated by plasma discharge of the gas, wherein the second nitride layer and the first nitride layer are prevented from being irradiated with ultraviolet rays generated at a time of the plasma discharge, and wherein the selectively removing the second nitride layer includes etching the second nitride layer under a first atmosphere at a first pressure that is lower than a first saturated vapor pressure of a silicon compound and that is higher than a second saturated vapor pressure of a gallium compound.

A field effect transistor, comprising a gate contact and gate metal forming a vertical structure, such vertical structure having sides and a top surrounded by an air gap formed between a source electrode and a drain electrode of the field effect transistor.

The present invention relates to an epitaxial structure of N-face group III nitride, its active device, and its gate protection device. The epitaxial structure of N-face AlGaN/GaN comprises a silicon substrate, a buffer layer (C-doped) on the silicon substrate, an i-GaN (C-doped) layer on the buffer layer (C-doped), an i-Al.sub.yGaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-Al.sub.yGaN buffer layer, and an i-Al.sub.xGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By connecting a depletion-mode (D-mode) AlGaN/GaN high electron mobility transistor (HEMT) to the gate of a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the gate of the p-GaN gate E-mode AlGaN/GaN HEMT can be protected under any gate voltage.

A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.