A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

A wafer processing method for processing a wafer formed on a front surface thereof with a plurality of devices having projection-shaped electrodes, the devices being partitioned by streets, includes a cutting step of holding a back surface of the wafer by a holding surface of a chuck table and cutting head portions of the projection-shaped electrodes by a cutting tool slewed in parallel to the holding surface, to make uniform the electrodes in height and expose metallic surfaces; a thermocompression bonding sheet laying step of laying a thermocompression bonding sheet on the front surface of the wafer; a thermocompression bonding step of heating and pressing the thermocompression bonding sheet to perform thermocompression bonding; and a peeling step of peeling off the thermocompression bonding sheet from the wafer, before dividing the wafer into individual device chips and bonding the electrodes to a circuit board.

The present description concerns an electronic die manufacturing method comprising: a) the deposition of an electrically-insulating resin layer on the side of a first surface of a semiconductor substrate, inside and on top of which have been previously formed a plurality of integrated circuits, the semiconductor substrate supporting on a second surface, opposite to the first surface, contacting pads; and b) the forming, on the side of the second surface of the semiconductor substrate, of first trenches, electrically separating the integrated circuits from one another, the first trenches vertically extending in the semiconductor substrate and emerging into or on top of the resin layer.

A laser processing device includes: a light source configured to output laser light; a space light modulator for modulating the laser light output from the light source in accordance with a modulation pattern and outputting the modulated laser light; a converging lens for converging the laser light output from the space light modulator to an object, and forming a converging spot on the object; a movement unit for relatively moving the converging spot with respect to the object; and a control unit for relatively moving, while setting a position of the converging spot in a Z direction intersecting with an incident surface of the laser light on the object at a first Z position, the converging spot along a line extended in an X direction along the incident surface by controlling at least the space light modulator and the movement unit.

A method for forming a semiconductor structure is provided. The method includes: providing a substrate; forming a groove in the substrate, in which a side wall of the groove is formed by sequential connection of a plurality of pits recessed into the substrate; forming a first material in the groove, in which the pits are completely filled with the first material; and exposing and developing the first material in the groove to obtain a through via structure.

A processing apparatus includes a chuck table for holding a workpiece, a processing unit for processing the workpiece held on the chuck table as supplying a processing water to the workpiece, and a water pan fixed to a bottom of the processing apparatus for receiving the processing water as a water leaked.

A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyester sheet, pushing up each device chip through the polyester sheet, and picking up each device chip from the polyester sheet.

The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The multi-dimensional integrated chip structure includes a first substrate having a first upper surface and a second upper surface above the first upper surface. A first outermost perimeter of the first upper surface is larger than a second outermost perimeter of the second upper surface. A second substrate is over the first substrate. The second substrate has a third upper surface above the second upper surface. A third outermost perimeter of the third upper surface is smaller than the second outermost perimeter of the second upper surface.

Structures and formation methods of a chip package structure are provided. The chip package structure includes adjacent first and second semiconductor dies bonded over an interposer substrate. The chip package structure also includes an insulating layer formed over the interposer substrate. The insulating layer has a first portion surrounding the first and second semiconductor dies and a second portion extending between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, and between the interposer substrate and the first and second semiconductor dies. The lateral distance from the top end of the first sidewall to the top end of the second sidewall is greater than the lateral distance from the bottom end of the first sidewall to the bottom end of the second sidewall.