The present invention relates to a method for manufacturing a sample for thin film property measurement and analysis, and a sample manufactured thereby and, more specifically, to: a method for manufacturing a sample capable of measuring or analyzing various properties in one sample; and a sample manufactured thereby.

The semiconductor device includes a mesa diode structure(20) and a protective layer(17b). The mesa diode structure includes, from bottom to top, a P-type semiconductor layer(11), a first N-type semiconductor layer(12), and a second N-type semiconductor layer(13) having a higher impurity concentration than the first N-type semiconductor layer. The protective layer is arranged on a side wall around the mesa diode structure seen in a plane. Specifically, the protective layer is arranged on an upper side surface(11c) of the P-type semiconductor layer and on side surfaces(12a,13a) of the first N-type semiconductor layer and the second N-type semiconductor layer, but is not arranged on a lower side surface of the P-type semiconductor layer. A bevel angle(30) of a PN junction plane between the P-type semiconductor layer and the first N-type semiconductor layer to the upper side surface of the P-type semiconductor layer is set to 85 to 120 degrees.

The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

Implementations of a method singulating a plurality of semiconductor die. Implementations may include: forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate where the semiconductor substrate includes a plurality of semiconductor die. The method may include etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer and jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die.

The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

A method for surface treatment of a workpiece made from a hard-brittle material comprises first blasting employing abrasive grains of higher hardness than a hardness of a base material of the workpiece for forming a three dimensional recess-protrusion profile having protrusions and recesses formed between the protrusions on a surface of the workpiece; and second blasting employing an elastic abrasive having a structure in which abrasive grains carried in and/or on an elastic body made from material with low rebound elasticity for polishing the surface of the workpiece formed with the recess-protrusion profile so as to achieve an arithmetic average roughness Ra of not greater than 1.6 μm on the surface of the protrusions and the recesses on the workpiece while maintaining the recess-protrusion profile formed by the first blasting.

Implementations of a method of singulating a plurality of semiconductor die may include forming an opening in a layer of passivation material coupled to a second side of a semiconductor substrate; etching substantially through a thickness of the semiconductor substrate at the opening in the layer of passivation material to form etched sidewalls along the thickness at a plurality of die streets; and jet ablating one or more portions of the layer of passivation material that overhangs the etched sidewalls.

The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

The present invention relates to a method for manufacturing a sample for thin film property measurement and analysis, and a sample manufactured thereby and, more specifically, to: a method for manufacturing a sample capable of measuring or analyzing various properties in one sample; and a sample manufactured thereby.

A monocrystalline semiconductor wafers have an average roughness R.sub.a of at most 0.8 nm at a limiting wavelength of 250 μm, and an ESFQR.sub.avg of 8 nm or less given an edge exclusion of 1 mm. The wafers are advantageously produced by a method comprising the following steps in the indicated order: a) simultaneous double-side polishing of the semiconductor wafer, b) local material-removing processing of at least one part of at least one side of the semiconductor wafer using a fluid jet which contains suspended hard substance particles and which is directed onto a small region of the surface with the aid of a nozzle, wherein the nozzle is moved over that part of the surface which is to be treated in such a way that a predefined geometry parameter of the semiconductor wafer is improved, and c) polishing of the at least one surface of the semiconductor wafer.