A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.

A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

A method comprises providing a substrate comprising an n-type Al/In/GaN semiconductor material. A surface of the substrate is dry-etched to form a trench therein and cause dry-etch damage to remain on the surface. The surface of the substrate is immersed in an electrolyte solution and illuminated with above bandgap light having a wavelength that generates electron-hole pairs in the n-type Al/In/GaN semiconductor material, thereby photoelectrochemically etching the surface to remove at least a portion of the dry-etch damage.

A semiconductor device includes a plurality of column portions including a semiconductor. The plurality of column portions each includes a source region, a drain region, and a channel formation region including a channel formed between the source region and the drain region. The semiconductor device further includes a gate electrode provided, via an insulating layer, at a side wall of the channel formation region, and also includes a first semiconductor layer provided at a side wall of the drain region. A conductive type of the first semiconductor layer differs from a conductive type of the semiconductor included in the drain region.

A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

Structures and related techniques for singulating GaN-on-Si wafers are disclosed. In one aspect, a semiconductor wafer includes a silicon layer, and a gallium nitride (GaN) layer disposed on the silicon layer and defining a plurality of trenches that each extend to the silicon layer. In another aspect, the GaN layer includes one or more gallium nitride layers of different compositions. In yet another aspect, the wafer includes a plurality of dielectric layers disposed on the GaN layer. In yet another aspect, each of the plurality of trenches has a depth that is equal to a sum of a thickness of the GaN layer and a thickness of the plurality of the dielectric layers.

A bonded semiconductor device including an epitaxial layer, and a support substrate made of a material different from that of the epitaxial layer and bonded to the epitaxial layer. Any one of the epitaxial layer and the support substrate has a bonding surface with a radial pattern including recesses or protrusions radially spreading from a certain point on the bonding surface as a center.

A bonded semiconductor light-receiving device including an epitaxial layer to serve as a device-functional layer, and a support substrate made of a material different from that of the device-functional layer and bonded to the epitaxial layer via a bonding material layer. The device-functional layer has a bonding surface with an uneven pattern formed thereon.

An integrated circuit structure comprises a silicon substrate and a III-nitride (III-N) substrate over the silicon substrate. A first III-N transistor and a second III-N transistor is on the III-N substrate. An insulator structure is formed in the III-N substrate between the first III-N transistor and the second III-N, wherein the insulator structure comprises one of: a shallow trench filled with an oxide, nitride or low-K dielectric; or a first gap adjacent to the first III-N transistor and a second gap adjacent to the second III-N transistor.

III-Nitride heterostructures with low p-type sheet resistance and III-Nitride heterostructure devices with gate recess and devices including the III-Nitride heterostructures are disclosed.