Patent classifications
H01L21/30625
POLISHING PAD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME
The present disclosure is intended to provide, as a polishing pad to which a window for an endpoint detection is applied, and in which the window is capable of providing improved polishing performance in terms of preventing defects, etc., by a specific structure due to the window, rather than negatively affecting polishing performance as a local heterogeneous component on the polishing pad, a polishing pad including: a polishing layer including a first surface that is a polishing surface and a second surface that is a rear surface thereof, and containing a first through-hole penetrating from the first surface to the second surface; a window disposed in the first through-hole; and a void between a side surface of the first through-hole and a side surface of the window, and a method for manufacturing a semiconductor device by applying the same.
SURFACE TREATMENT METHOD, METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE INCLUDING THE SURFACE TREATMENT METHOD, COMPOSITION FOR SURFACE TREATMENT, AND SYSTEM FOR PRODUCING SEMICONDUCTOR SUBSTRATE INCLUDING THE COMPOSITION FOR SURFACE TREATMENT
The present invention provides a means capable of sufficiently removing a residue containing inorganic oxide abrasive grains present on the surface of a polished object to be polished containing silicon nitride. One aspect of the present invention relates to a surface treatment method for reducing a residue containing inorganic oxide abrasive grains on a surface of a polished object to be polished containing silicon nitride using a composition for surface treatment, wherein the composition for surface treatment contains a zeta potential adjusting agent having a negatively charged functional group and having a viscosity of an aqueous solution having a concentration of 20% by mass at 25° C. of 10 mPa.Math.s or more and a dispersing medium, and the surface treatment method includes controlling a zeta potential of the silicon nitride and a zeta potential of the inorganic oxide abrasive grains each to −30 mV or less using the composition for surface treatment.
Polishing pad and method for manufacturing same
The present invention addresses the problem of providing: a polishing pad that is long-lasting, has a high polish rate, and is capable of producing a high degree of flatness on polished articles; and a method for manufacturing the polishing pad. The solution provided is to eliminate a sea component from a non-woven fabric that includes a binder fabric and a sea-island type composite fiber composed of the sea component and an island component, the island component having a diameter of 10-2500 nm, and to add a polymer elastic body to the non-woven fabric.
Cationic fluoropolymer composite polishing method
The invention provides a method for polishing or planarizing a substrate of at least one of semiconductor, optical and magnetic substrates. The method includes attaching a polymer-polymer composite polishing pad having a polishing layer to a polishing device. A hydrophilic polymeric matrix forms the polishing layer. Cationic fluoropolymer particles having nitrogen-containing end groups are embedded in the polymeric matrix. A slurry containing anionic particles is applied to the polymer-polymer composite polishing pad and rubbed against the substrate to polish or planarize the substrate with the fluoropolymer particles interacting with the anionic particles to increase polishing removal rate.
METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND METHOD OF SEPARATING SUBSTRATE
Disclosed are methods of fabricating semiconductor devices and methods of separating substrates. The semiconductor device fabricating method comprises providing a release layer between a carrier substrate and a first surface of a device substrate to attach the device substrate to the carrier substrate, irradiating the carrier substrate with an ultraviolet ray to separate the carrier substrate from the release layer and to expose one surface of the release layer, and performing a cleaning process on the one surface of the release layer to expose the first surface of the device substrate. The release layer includes an aromatic polymerization unit and a siloxane polymerization unit.
Protective wafer grooving structure for wafer thinning and methods of using the same
A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
APPARATUS AND METHODS OF FORMING FIN STRUCTURES WITH ASYMMETRIC PROFILE
An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.
Detecting an excursion of a CMP component using time-based sequence of images and machine learning
Monitoring operations of a polishing system includes obtaining a time-based sequence of reference images of a component of the polishing system performing operations during a test operation of the polishing system, receiving from a camera a time-based sequence of monitoring images of an equivalent component of an equivalent polishing system performing operations during polishing of a substrate, determining a difference value for the time-based sequence of monitoring images by comparing the time-based sequence of reference images to the time-based sequence of monitoring image using an image processing algorithm, determining whether the difference value exceeds a threshold, and in response to determining the difference value exceeds the threshold, indicating an excursion.
PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING A PHASE OF FORMING TRENCHES IN A SUBSTRATE AND CORRESPONDING INTEGRATED CIRCUIT
Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.
WAFER PROCESSING TEMPORARY ADHESIVE, WAFER LAMINATE, THIN WAFER MANUFACTURING METHOD
Provided are: a wafer processing temporary adhesive that is for temporarily adhering a wafer to a support and that comprises a thermosetting resin composition containing a non-functional organopolysiloxane; a wafer laminate; and a thin wafer manufacturing method.