Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a gate is firstly formed in a gate region of a first trench, then an n-type epitaxial layer is etched with a hard mask layer and an insulating side wall covering a side wall of the gate as masks, and a second trench is formed in the n-type epitaxial layer, and then a p-type column is formed in the first trench and the second trench.

Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

A semiconductor structure includes a substrate having a trench array therein, wherein the trench array includes a plurality of outer trenches and a plurality of inner trenches, wherein each of the plurality of outer trenches has a width greater than a width of each of the plurality of inner trenches. The semiconductor structure further includes a capacitor material stack extending into the trench array.

A semiconductor structure includes a substrate having a trench array therein, wherein the trench array includes a plurality of outer trenches and a plurality of inner trenches, wherein each of the plurality of outer trenches has a width greater than a width of each of the plurality of inner trenches. The semiconductor structure further includes a capacitor material stack extending into the trench array.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Integrated circuit devices and methods of forming the same are provided. The methods may include sequentially forming an underlying mask layer and a preliminary first mask layer on a substrate, forming a first mask structure by removing a portion of the preliminary first mask layer, and then forming a preliminary second mask layer. The preliminary second mask layer may enclose the first mask structure in a plan view. The methods may also include forming a second mask structure by removing a portion of the preliminary second mask layer and forming a vertical channel region including a portion of the substrate by sequentially etching the underlying mask layer and the substrate. The second mask structure may be connected to the first mask structure, and etching the underlying mask layer may be performed using the first and the second mask structures as an etch mask.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

Embodiments described herein relate to methods forming optical device structures. One embodiment of the method includes exposing a substrate to ions at an ion angle relative to a surface normal of a surface of the substrate to form an initial depth of a plurality of depths. A patterned mask is disposed over the substrate and includes two or more projections defining exposed portions of the substrate or a device layer disposed on the substrate. Each projection has a trailing edge at a bottom surface contacting the device layer, a leading edge at a top surface of each projection, and a height from the top surface to the device layer. Exposing the substrate to ions at the ion angle is repeated to form at least one subsequent depth of the plurality of depths.

A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels.