A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Integrated circuit devices and methods of forming the same are provided. The methods may include sequentially forming an underlying mask layer and a preliminary first mask layer on a substrate, forming a first mask structure by removing a portion of the preliminary first mask layer, and then forming a preliminary second mask layer. The preliminary second mask layer may enclose the first mask structure in a plan view. The methods may also include forming a second mask structure by removing a portion of the preliminary second mask layer and forming a vertical channel region including a portion of the substrate by sequentially etching the underlying mask layer and the substrate. The second mask structure may be connected to the first mask structure, and etching the underlying mask layer may be performed using the first and the second mask structures as an etch mask.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels.

Methods for selectively etching SiGe relative to Si are provided. Some of the methods incorporate formation of a passivation layer on a surface of the Si layer to enhance SiGe etchant selectivity and the use of interhalogen gases that preferentially etch the SiGe as opposed to the Si in the presence of the passivation layer. The methods can occur in a cyclic manner until the desired thickness of the SiGe layer is obtained.

A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.

A method for manufacturing a semiconductor device includes: a first insulating film forming step of forming a first insulating film in a transistor having a structure in which a source and a drain raised in a fin shape are covered with a gate; a sacrifice film forming step of forming a sacrifice film; a hard mask pattern forming step of forming a hard mask film having a desired pattern; a first opening forming step of forming a first opening; a second insulating film forming step of forming a second insulating film made of a material different from the first insulating film, in the first opening; a second opening forming step of forming a second opening by removing the sacrifice film, after the second insulating film forming step; and a contact plug forming step of forming a contact plug in the second opening.

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region; disposing an insulating layer over the substrate; disposing a capping layer over the insulating layer; disposing a hardmask stack on the capping layer; patterning the hardmask stack; removing portions of the capping layer exposed through the hardmask stack; removing portions of the insulating layer exposed through the hardmask stack; removing portions of the substrate exposed through the capping layer and the insulating layer to form a plurality of fins in the array area and a first elongated member at least partially surrounding the plurality of fins; removing the hardmask stack; and forming an isolation over the substrate and surrounding the plurality of fins and the first elongated member.