A method for etching a tungsten silicide (WSix) layer during formation of a gate electrode in an integrated circuit is disclosed. The method uses an etchant gas comprising nitrogen gas (N.sub.2) and oxygen gas (O.sub.2) in a specified flow ratio. The etchant gas may also comprise chlorine gas (Cl.sub.2) and tetrafluoromethane (CF.sub.4). The selectivity of the etchant gas containing O.sub.2 for WSix versus polysilicon is much higher, which reduces overetching and provides more control in methods for producing a gate electrode. A gate electrode produced by such a method is also disclosed.

A variety of applications can include apparatus having a memory device with an array of vertical strings of memory cells for the memory device with data lines coupled to the vertical strings, where the data lines have been formed by a metal liner deposition process. In the metal liner deposition, a metal can be formed on a patterned dielectric region. The metal liner deposition process allows for construction of the height of the data lines to be well controlled with selection of a thickness for the dielectric region used in forming the metal liner. Use of a metal liner deposition provides a controlled mechanism to reduce data line capacitance by being able to select liner thickness in forming the data lines. The use of the dielectric region with the metal liner deposition can allow the fabrication of the data lines to avoid pitch double or pitch quad processes.

A semiconductor device includes active regions extending in a first direction on a substrate; a gate electrode intersecting the active regions on the substrate, extending in a second direction, and including a contact region protruding upwardly; and an interconnection line on the gate electrode and connected to the contact region, wherein the contact region includes a lower region having a first width in the second direction and an upper region located on the lower region and having a second width smaller than the first width in the second direction, and wherein at least one side surface of the contact region in the second direction has a point at which an inclination or a curvature is changed between the lower region and the upper region.

An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

Semiconductor device is provided. The semiconductor device includes a base substrate including a first region, a second region, and a third region arranged along a first direction, a first doped layer in the base substrate at the first region and a second doped layer in the base substrate at the third region, a first gate structure on the base substrate at the second region, a first dielectric layer on the base substrate coving the first doped layer, the second doped layer, and sidewalls of the first gate structure, first trenches in the first dielectric layer at the first region and the third region respectively, a first conductive layer in the first trenches, a second conductive layer on a surface of the first conductive layer at the second sub-regions after forming the first conductive layer, and a third conductive layer on the contact region of the first gate structure.

An etching method is provided. In the etching method, a protective film-forming gas including an amine gas is supplied to a substrate having a surface on which a first film and a second film are formed, the first film and the second film having respective properties of being etched by an etching gas, and a protective film is formed to cover the first film such that the first film is selectively protected between the first film and the second film when the etching gas is supplied. Further, the second film is selectively etched by supplying the etching gas to the substrate after the protective film is formed.

Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

In certain embodiments, a method of processing a semiconductor structure includes forming a patterned layer over a copper layer to be etched. The copper layer is disposed over a substrate. The method includes patterning the copper layer, using the patterned layer as an etch mask, by performing a cyclic etch process to form a recess in the copper layer. The cyclic etch process includes forming, in a first etch step, a passivation layer on an exposed surface of the copper layer by exposing the exposed surface of the copper layer to a chlorine gas. The passivation layer replaces at least a portion of a surface layer of the copper layer. The cyclic etch process includes subsequently etching, in a second etch step, the passivation layer using a first plasma that includes a noble gas. Each cycle of the cyclic etch process extends the recess in the copper layer.

A method of processing a substrate is provided. The substrate includes an etching target region and a patterned region. The patterned region is provided on the etching target region. In the method, an organic film is formed on a surface of the substrate. Subsequently, the etching target region is etched by plasma generated from a processing gas. The organic film is formed in a state that the substrate is placed in a processing space within a chamber. When the organic film is formed, a first gas containing a first organic compound is supplied toward the substrate, and then, a second gas containing a second organic compound is supplied toward the substrate. An organic compound constituting the organic film is generated by polymerization of the first organic compound and the second organic compound.