A method for etching a tungsten silicide (WSix) layer during formation of a gate electrode in an integrated circuit is disclosed. The method uses an etchant gas comprising nitrogen gas (N.sub.2) and oxygen gas (O.sub.2) in a specified flow ratio. The etchant gas may also comprise chlorine gas (Cl.sub.2) and tetrafluoromethane (CF.sub.4). The selectivity of the etchant gas containing O.sub.2 for WSix versus polysilicon is much higher, which reduces overetching and provides more control in methods for producing a gate electrode. A gate electrode produced by such a method is also disclosed.

A semiconductor device includes active regions extending in a first direction on a substrate; a gate electrode intersecting the active regions on the substrate, extending in a second direction, and including a contact region protruding upwardly; and an interconnection line on the gate electrode and connected to the contact region, wherein the contact region includes a lower region having a first width in the second direction and an upper region located on the lower region and having a second width smaller than the first width in the second direction, and wherein at least one side surface of the contact region in the second direction has a point at which an inclination or a curvature is changed between the lower region and the upper region.

An etching method is provided. In the etching method, a protective film-forming gas including an amine gas is supplied to a substrate having a surface on which a first film and a second film are formed, the first film and the second film having respective properties of being etched by an etching gas, and a protective film is formed to cover the first film such that the first film is selectively protected between the first film and the second film when the etching gas is supplied. Further, the second film is selectively etched by supplying the etching gas to the substrate after the protective film is formed.

A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.

A semiconductor fabricating method for a film to be processed containing a transition metal on an upper surface of a semiconductor wafer placed in a processing chamber in a container being etched with a gas for complexing the transition metal supplied into the processing chamber, including a first step of adsorbing, to the film, the complexing gas, while supplying the complexing gas, then increasing a temperature of the wafer to form an organic metal complex on a surface of the film, and volatilizing and desorbing the organic metal complex, and a second step of adsorbing, to the surface of the film, the complexing gas at a low temperature, while supplying the complexing gas, then stopping the supply of the complexing gas, and stepwise increasing the temperature of the wafer to volatilize and desorb an organic metal complex formed on the surface of the film.

An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.

The present application provides a method for process a substrate. The method includes steps of providing a substrate having a sacrificial layer and an insulative layer, forming a polysilicon hardmask on the insulative layer, etching the insulative and sacrificial layers through multiple openings in the polysilicon hardmask to thus form multiple channels, depositing a metal film and a passivation film on the polysilicon hardmask and in the channels, performing a first removal process to remove portions of the passivation film and the metal film above the polysilicon hardmask, performing a second removal process to remove portions of the polysilicon hardmask exposed through the passivation film and the metal film, and performing a third removal process to remove the polysilicon hardmask and portions of the passivation film and the metal film surrounding the polysilicon is hardmask.

The present application provides a method for manufacturing a capacitor array. The method includes steps of depositing a sacrificial layer on a bottom electrode; depositing an insulative layer on the sacrificial layer; forming a polysilicon hardmask on the insulative layer; etching the insulative layer and the sacrificial layer exposed through a plurality of openings in the polysilicon hardmask to form channels; depositing a metal film on the polysilicon hardmask and in the channels; depositing a passivation film on the metal film; depositing a conductive material in the channels and in contact with the insulative layer and the sacrificial layer; removing the sacrificial layer; and forming a top electrode on the insulative layer.

A semiconductor manufacturing method using a semiconductor manufacturing apparatus 100 including a treating chamber 1, the method including: a first process of supplying a complexing gas into the treating chamber in which a wafer 2 having a surface having a transition metal-containing film formed thereon is placed, to adsorb an organic compound as a component of the complexing gas to the transition metal-containing film, the transition metal-containing film containing a transition metal element; and a second process of heating the wafer in which the organic compound is adsorbed to the transition metal-containing film, to react the organic compound with the transition metal element, thereby converting the organic compound into an organometallic complex, and desorbing the organometallic complex, wherein the organic compound has Lewis basicity, and is a multidentate ligand molecule capable of forming a bidentate or more coordination bond with the transition metal element.