A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.

A method of manufacturing nitride semiconductor substrate, comprising: providing silicon-on-insulator substrate which comprises an underlying silicon layer, a buried silicon dioxide layer and a top silicon layer; forming a first nitride semiconductor layer on the top silicon layer; forming, in the first nitride semiconductor layer, a plurality of notches which expose the top silicon layer; removing the top silicon layer and forming a plurality of protrusions and a plurality of recesses on an upper surface of the buried silicon dioxide layer, wherein each of the plurality of protrusions is in contact with the first nitride semiconductor layer, and there is a gap between each of the plurality of recesses and the first nitride semiconductor layer; and epitaxially growing a second nitride semiconductor layer on the first nitride semiconductor layer, such that the first nitride semiconductor layer and the second nitride semiconductor layer form a nitride semiconductor substrate.

A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.

A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.

A semiconductor device includes: a compound semiconductor layer having a first compound semiconductor layer and a second compound semiconductor layer having a higher melting point than the first compound semiconductor layer; and an insulation gate on the second compound semiconductor layer. The compound semiconductor layer further includes: a drift region; a source region; and a body region between the drift region and the source region. The insulation gate faces the body region. The body region bridges over both the first compound semiconductor layer and the second compound semiconductor layer.

A manufacturing method of a nitride semiconductor device includes: introducing a p type impurity into at least a part of an upper layer portion of a first nitride semiconductor layer to form a p type impurity introduction region; forming a second nitride semiconductor layer from an upper surface of the first nitride semiconductor layer so as to include the p type impurity introduction region; and performing an anneal treatment in a state where the second nitride semiconductor layer is formed on the first nitride semiconductor layer.

A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

A semiconductor device and fabricating method thereof is disclosed. The method comprises depositing epitaxial layers over a silicon substrate to form a semiconductor layer surface; forming at least one mesa portion on the semiconductor layer surface; depositing a metal stack on the semiconductor layer surface; subjecting the semiconductor layer surface to a rapid thermal annealing system for a two-step ohmic contact annealing in H.sub.2/N.sub.2 forming gas (FG) and then nitrogen; subjecting the semiconductor layer surface to an oxygen plasma treatment; and depositing a T-shaped metal gate on the semiconductor layer surface. A semiconductor device comprises a semiconductor layer surface having an epitaxial layer disposed over a silicon substrate; at least one mesa portion formed on the semiconductor layer surface; a metal stack, disposed on the semiconductor layer surface, and sequentially annealed in FG and nitrogen; and a T-shaped metal gate on the semiconductor layer surface.

A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.