An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

A method for manufacturing a semiconductor device is provided. The method includes forming an organosilicon compound layer on a surface of an oxide semiconductor substrate, heating the oxide semiconductor substrate provided with the organosilicon compound layer at a first temperature to form a silicon diffusion layer inside the oxide semiconductor substrate, and removing the organosilicon compound layer from the surface of the oxide semiconductor substrate after heating the oxide semiconductor substrate at the first temperature.

A thin film transistor, an array substrate and a display device are disclosed, the thin film transistor comprises a gate electrode, an active layer located on the gate electrode, and a source electrode and a drain electrode respectively located at opposite sides of the active layer and both partially overlapped with the active layer; the active layer includes at least one first structure part and at least one second structure part, a material for the first structure part is semiconductor, and a material for the second structure part is predetermined conductor, and the predetermined conductor has better conductivity than the conductivity of the conducted semiconductor, and in response to that a turn-on voltage is applied to the gate electrode, a conductive passage located between the source electrode and the drain electrode includes the first structure part and the second structure part.

A wafer-level manufacturing method for embedding a passive element in a glass substrate is disclosed. A highly doped silicon wafer is dry etched to form a highly doped silicon mould wafer, containing highly doped silicon passive component structures mould seated in cavity arrays; a glass wafer is anodically bonded to the highly doped silicon mould wafer in vacuum pressure to seal the cavity arrays; the bonded wafers are heated so that the glass melts and fills gaps in the cavity arrays, annealing and cooling are performed, and a reflowed wafer is formed; the upper glass substrate of the reflowed wafer is grinded and polished to expose the highly doped silicon passives; the passive component structure mould embedded in the glass substrate is fully etched; the blind holes formed in the glass substrates after the passive component structure mould has been etched is filled with copper by electroplating; the highly doped silicon substrate and unetched silicon between the cavity arrays are etched, and several glass substrates embedded with a passive element are obtained; to form electrodes for the passives, a metal adhesion layer is deposited, and a metal conductive layer is electroplated. The process is simple, costs are low, and the prepared passive elements have superior performance.

A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region. A memory layer is formed on surfaces of the strip in the memory region. A plurality of memory cell gates is formed over the memory region of the strip. A switch gate is formed over the switch region of the strip. A doped insulating material is deposited over a portion of the strip between the contact landing area region and the memory region. Diffusion of dopant is caused from the doped insulating material into the strip in the portion of the strip.

A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.

Disclosed herein is a method that includes forming a gate electrode on an active region of a semiconductor substrate surrounded by a STI region; implanting a first dopant into the active region by using the gate electrode as a mask to form LDD regions; forming a liner film on top and side surfaces of the gate electrode, the STI region, and the LDD regions; forming a side wall spacer on the side surfaces of the gate electrode with the liner film interposed therebetween; implanting, with covering the STI region and the LDD regions by the liner film, a second dopant by using the gate electrode, the liner film formed on the side surfaces of the gate electrode, and the side wall spacer as a mask to form source/drain regions; and removing the side wall spacer.

Disclosed herein is a method that includes forming a gate electrode on an active region of a semiconductor substrate surrounded by a STI region; implanting a first dopant into the active region by using the gate electrode as a mask to form LDD regions; forming a liner film on top and side surfaces of the gate electrode, the STI region, and the LDD regions; forming a side wall spacer on the side surfaces of the gate electrode with the liner film interposed therebetween; implanting, with covering the STI region and the LDD regions by the liner film, a second dopant by using the gate electrode, the liner film formed on the side surfaces of the gate electrode, and the side wall spacer as a mask to form source/drain regions; and removing the side wall spacer.

A solar cell includes: a semiconductor substrate which includes a first principal surface and a second principal surface; a first semiconductor layer of the first conductivity type disposed above the first principal surface; and a second semiconductor layer of a second conductivity type disposed below the second principal surface. The semiconductor substrate includes: a first impurity region of the first conductivity type; a second impurity region of the first conductivity type disposed between the first impurity region and the first semiconductor layer; and a third impurity region of the first conductivity type disposed between the first impurity region and the second semiconductor layer. A concentration of an impurity in the second impurity region is higher than a concentration of the impurity in the third impurity region, and the concentration of the impurity in the third impurity region is higher than a concentration of the impurity in the first impurity region.