H01L21/385

INSULATING FILM, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm.sup.2 and lower than or equal to 0.5 W/cm.sup.2 is supplied to an electrode provided in the treatment chamber.

INSULATING FILM, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm.sup.2 and lower than or equal to 0.5 W/cm.sup.2 is supplied to an electrode provided in the treatment chamber.

COMPOSITE SUBSTRATE AND MANUFACTURING METHOD THEREOF
20220393003 · 2022-12-08 ·

A composite substrate is provided in some embodiments of the present disclosure, which includes a substrate, an insulation layer, a first silicon-containing layer and a first epitaxial layer. The insulation layer is disposed on the substrate. The first silicon-containing layer is disposed on the insulation layer, in which the first silicon-containing layer includes a plurality of group V atoms. The first epitaxial layer is disposed on the first silicon-containing layer, in which the first epitaxial layer includes a plurality of group III atoms. A distribution concentration of the group V atoms in the first silicon-containing layer increases as getting closer to the first epitaxial layer, and a distribution concentration of the group III atoms in the first epitaxial layer increases as getting closer to the first silicon-containing layer. A method of manufacturing a composite substrate is also provided in some embodiments of the present disclosure.

Method for doping using electric field

A doping method using an electric field includes stacking a sacrificial layer on a doped layer, disposing a doping material on the sacrificial layer, disposing electrodes on the doping material and the doped layer, respectively, and doping the doping material into the doped layer through oxidation, diffusion, and reduction of the doping material by the electric field.

Semiconductor device and manufacturing method thereof

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.

Semiconductor device and manufacturing method thereof

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.

Composite substrate and manufacturing method thereof
11600706 · 2023-03-07 · ·

A composite substrate is provided in some embodiments of the present disclosure, which includes a substrate, an insulation layer, a first silicon-containing layer and a first epitaxial layer. The insulation layer is disposed on the substrate. The first silicon-containing layer is disposed on the insulation layer, in which the first silicon-containing layer includes a plurality of group V atoms. The first epitaxial layer is disposed on the first silicon-containing layer, in which the first epitaxial layer includes a plurality of group III atoms. A distribution concentration of the group V atoms in the first silicon-containing layer increases as getting closer to the first epitaxial layer, and a distribution concentration of the group III atoms in the first epitaxial layer increases as getting closer to the first silicon-containing layer. A method of manufacturing a composite substrate is also provided in some embodiments of the present disclosure.

Method for manufacturing semiconductor device
11646208 · 2023-05-09 · ·

A method for manufacturing a semiconductor device is provided. The method includes forming an organosilicon compound layer on a surface of an oxide semiconductor substrate, heating the oxide semiconductor substrate provided with the organosilicon compound layer at a first temperature to form a silicon diffusion layer inside the oxide semiconductor substrate, and removing the organosilicon compound layer from the surface of the oxide semiconductor substrate after heating the oxide semiconductor substrate at the first temperature.

Method for manufacturing semiconductor device
11646208 · 2023-05-09 · ·

A method for manufacturing a semiconductor device is provided. The method includes forming an organosilicon compound layer on a surface of an oxide semiconductor substrate, heating the oxide semiconductor substrate provided with the organosilicon compound layer at a first temperature to form a silicon diffusion layer inside the oxide semiconductor substrate, and removing the organosilicon compound layer from the surface of the oxide semiconductor substrate after heating the oxide semiconductor substrate at the first temperature.

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE INCLUDING SAME
20170363893 · 2017-12-21 ·

Provided is a semiconductor device having a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode, and also provided region method for manufacturing the same and a display device including the same.

A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20s) or a drain region (20d) can be reduced, resulting in diminished parasitic capacitance.