A two-dimensional semiconductor transistor includes a gate electrode, a gate insulating layer disposed on the gate electrode, an organic dopant layer disposed on the gate insulating layer and comprising an organic material including electrons, a two-dimensional semiconductor layer disposed on the organic dopant layer, a source electrode disposed on the two-dimensional semiconductor layer, and a drain electrode disposed on the two-dimensional semiconductor layer and spaced apart from the source electrode. A hysteresis of the two-dimensional semiconductor transistor is reduced due to the two-dimensional semiconductor transistor including the organic dopant layer.

A two-dimensional semiconductor transistor includes a gate electrode, a gate insulating layer disposed on the gate electrode, an organic dopant layer disposed on the gate insulating layer and comprising an organic material including electrons, a two-dimensional semiconductor layer disposed on the organic dopant layer, a source electrode disposed on the two-dimensional semiconductor layer, and a drain electrode disposed on the two-dimensional semiconductor layer and spaced apart from the source electrode. A hysteresis of the two-dimensional semiconductor transistor is reduced due to the two-dimensional semiconductor transistor including the organic dopant layer.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A plating chuck for holding a substrate during plating processes, wherein the substrate has a notch area (3031) and a patterned region (3032) adjacent to the notch area (3031). The plating chuck comprises a cover plate (3033) configured to cover the notch area (3031) of the substrate to shield the electric field at the notch area (3031) when the substrate is being plated.

A plating chuck for holding a substrate during plating processes, wherein the substrate has a notch area (3031) and a patterned region (3032) adjacent to the notch area (3031). The plating chuck comprises a cover plate (3033) configured to cover the notch area (3031) of the substrate to shield the electric field at the notch area (3031) when the substrate is being plated.

A semiconductor device (200A) includes: a thin film transistor (201) including a gate electrode (3), an oxide semiconductor layer (5), a gate insulating layer (4), and a source electrode (7S) and a drain electrode (7D); an interlayer insulating layer (11) arranged so as to cover the thin film transistor (201) and to be in contact with a channel region (5c) of the thin film transistor (201); a transparent conductive layer (19) arranged on interlayer insulating layer (11), wherein: the source and drain electrodes (7) each include copper; a copper alloy oxide film (10) including copper and at least one metal element other than copper is arranged between the source and drain electrodes (7) and the interlayer insulating layer (11); the interlayer insulating layer (11) covers the drain electrode (7D) with the copper alloy oxide film (10) interposed therebetween; and in a contact hole (CH1) formed in the interlayer insulating layer (11), the transparent conductive layer (19) is in direct contact with the drain electrode (7D) without the copper alloy oxide film (10) interposed therebetween.

A semiconductor device (200A) includes: a thin film transistor (201) including a gate electrode (3), an oxide semiconductor layer (5), a gate insulating layer (4), and a source electrode (7S) and a drain electrode (7D); an interlayer insulating layer (11) arranged so as to cover the thin film transistor (201) and to be in contact with a channel region (5c) of the thin film transistor (201); a transparent conductive layer (19) arranged on interlayer insulating layer (11), wherein: the source and drain electrodes (7) each include copper; a copper alloy oxide film (10) including copper and at least one metal element other than copper is arranged between the source and drain electrodes (7) and the interlayer insulating layer (11); the interlayer insulating layer (11) covers the drain electrode (7D) with the copper alloy oxide film (10) interposed therebetween; and in a contact hole (CH1) formed in the interlayer insulating layer (11), the transparent conductive layer (19) is in direct contact with the drain electrode (7D) without the copper alloy oxide film (10) interposed therebetween.

According to one embodiment, a substrate processing apparatus includes a table configured to place a substrate thereon and to connect the substrate to a positive electrode, an counter electrode located opposite to the table, having a plurality of holes, and connected to a negative electrode, and a holding unit located opposite to the table across the counter electrode and configured to supply a chemical liquid to the counter electrode while holding the counter electrode.

According to one embodiment, a substrate processing apparatus includes a table configured to place a substrate thereon and to connect the substrate to a positive electrode, an counter electrode located opposite to the table, having a plurality of holes, and connected to a negative electrode, and a holding unit located opposite to the table across the counter electrode and configured to supply a chemical liquid to the counter electrode while holding the counter electrode.