Methods and apparatus for increasing a bonded area between an ultrathin die and a substrate. In some embodiments, the method may include cleaning the die and the substrate, placing the die on an upper surface of the substrate, compacting the die to the substrate using a downward force of at least one compacting roller on the die and the upper surface of the substrate to increase a bonded area between the die and the upper surface of the substrate, and annealing the die and the substrate. The compacting roller has a soft surface layer that engages with the die and the upper surface of the substrate. The soft surface layer has a Shore hardness of greater than approximately 30 and less than approximately 80. In some embodiments, the substrate and/or the compacting roller may rotate during contact with each other.

Methods and apparatus for increasing a bonded area between an ultrathin die and a substrate. In some embodiments, the method may include cleaning the die and the substrate, placing the die on an upper surface of the substrate, compacting the die to the substrate using a downward force of at least one compacting roller on the die and the upper surface of the substrate to increase a bonded area between the die and the upper surface of the substrate, and annealing the die and the substrate. The compacting roller has a soft surface layer that engages with the die and the upper surface of the substrate. The soft surface layer has a Shore hardness of greater than approximately 30 and less than approximately 80. In some embodiments, the substrate and/or the compacting roller may rotate during contact with each other.

A manufacturing method of a semiconductor structure includes at least the following steps. A patterned mask layer with a first opening is formed on a dielectric layer overlying a semiconductor substrate. A portion of the dielectric layer accessibly exposed by the first opening of the patterned mask layer is removed to form a second opening. A first protective film is formed on inner sidewalls of the dielectric layer and the patterned mask layer, where the second opening and the first protective film are formed at the same step. A second protective film is formed on the first protective film to form a protective structure covering the inner sidewalls. A portion of the semiconductor substrate accessibly exposed by the second opening is removed to form a via hole including an undercut underlying the protective structure. The via hole is trimmed and a through substrate via is formed in the via hole.

A manufacturing method of a semiconductor structure includes at least the following steps. A patterned mask layer with a first opening is formed on a dielectric layer overlying a semiconductor substrate. A portion of the dielectric layer accessibly exposed by the first opening of the patterned mask layer is removed to form a second opening. A first protective film is formed on inner sidewalls of the dielectric layer and the patterned mask layer, where the second opening and the first protective film are formed at the same step. A second protective film is formed on the first protective film to form a protective structure covering the inner sidewalls. A portion of the semiconductor substrate accessibly exposed by the second opening is removed to form a via hole including an undercut underlying the protective structure. The via hole is trimmed and a through substrate via is formed in the via hole.

The present invention is an IC chip mounting apparatus including: a conveyor configured to convey an antenna continuous body on a conveying surface, the antenna continuous body having a base material and plural inlay antennas continuously formed on the base material; an IC chip placement unit configured to place an IC chip on a photo-curable adhesive that is located on a reference position of each antenna in the antenna continuous body; and a light irradiator configured to irradiate, with light, the adhesive of each antenna of the antenna continuous body that is conveyed by the conveyor, wherein the light irradiator is configured to irradiate the adhesive of each antenna with the light, while the IC chip on the adhesive is pressed to the antenna.

The present invention is an IC chip mounting apparatus including: a conveyor configured to convey an antenna continuous body on a conveying surface, the antenna continuous body having a base material and plural inlay antennas continuously formed on the base material; an IC chip placement unit configured to place an IC chip on a photo-curable adhesive that is located on a reference position of each antenna in the antenna continuous body; and a light irradiator configured to irradiate, with light, the adhesive of each antenna of the antenna continuous body that is conveyed by the conveyor, wherein the light irradiator is configured to irradiate the adhesive of each antenna with the light, while the IC chip on the adhesive is pressed to the antenna.

A method for preparing precise pattern of integrated circuits, which comprises the following steps: (S1) preparing a large pitch trench or circular through-hole structure with a hard mask in a first dielectric layer by lithography and etching; (S2) forming micro trench on the hard mask of the second dielectric layer at the bottom side wall of the trench or circular through-hole structure by plasma etching process; (S3) removing the first dielectric layer; (S4) opening the hard mask of the second dielectric layer at the micro trench formed on the hard mask of the second dielectric layer by plasma etching process; (S5) small pitch trench or circular through holes are prepared in the second dielectric layer.

A method for preparing precise pattern of integrated circuits, which comprises the following steps: (S1) preparing a large pitch trench or circular through-hole structure with a hard mask in a first dielectric layer by lithography and etching; (S2) forming micro trench on the hard mask of the second dielectric layer at the bottom side wall of the trench or circular through-hole structure by plasma etching process; (S3) removing the first dielectric layer; (S4) opening the hard mask of the second dielectric layer at the micro trench formed on the hard mask of the second dielectric layer by plasma etching process; (S5) small pitch trench or circular through holes are prepared in the second dielectric layer.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.