The present invention provides a QFN packaging structure and QFN packaging method. By providing the insulating layer on the outer side of the leads of the QFN packaging structure, a short circuit between the leads and the electromagnetic shielding layer can be prevented. In addition, the grounding lead is exposed from the insulating layer, such that the electromagnetic shielding layer is grounded via the grounding lead, thereby realizing the electromagnetic shielding design of the QFN packaging structure.

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.

The present invention relates to a silicon etching composition, and to a composition for selectively etching silicon with respect to a silicon insulating film.

The etching composition according to the present invention can improve the selective etching ratio of silicon from the surface of the semiconductor on which a silicone oxide film and silicon are exposed.

A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple source/drain segments each connected to corresponding ones of the channel sub-layers.

According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.

A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple source/drain segments each connected to corresponding ones of the channel sub-layers.

A fluid sampler includes: a sample cell that includes: a substrate comprising: a first port; a second port in fluid communication with the first port; a viewing reservoir in fluid communication with the first port and the second port and that receives the fluid from the first port and communicates the fluid to the second port, the viewing reservoir including: a first view membrane; a second view membrane; and a pillar interposed between the first view membrane and second view membrane, the pillar separating the first view membrane from the second view membrane at a substantially constant separation distance such that a volume of the viewing reservoir is substantially constant and invariable with respect to a temperature and invariable with respect to a pressure to which the sample cell is subjected.