A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of high manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

A method and system for forming material within a gap on a surface of a substrate using metal material are disclosed. An exemplary method includes forming a layer of meltable material overlying the substrate and heating the meltable material to a flow temperature to form molten material that flows within the gap.

A method of fabricating an integrated circuit structure comprises depositing an oxide insulator layer over a substrate having fins. A gate trench is formed within the oxide insulator layer with the fins extending above a surface of the oxide insulator layer within the gate trench. A semiconducting oxide material is deposited to conformally cover the oxide insulator layer, including on top surfaces and sidewalls of both the gate trench and the fins. A gate material is deposited to conformally cover the semiconducting oxide material, including on top surfaces and sidewalls of both the gate trench and the fins. An angled etch is performed to remove the gate material selective to the semiconducting oxide material from sidewalls of the gate trench, but not from sidewalls of the fins.

There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.

Disclosed are a thin-film transistor and a preparation method therefor, and a display substrate and a display panel. The thin-film transistor includes: a base substrate; an active layer located on the base substrate; and a source-drain electrode which is located on the side of the active layer facing away from the base substrate, and includes an electrode layer and a protective layer, where the material of the electrode layer includes a first metal element; the protective layer covers the surface of the side of the electrode layer facing away from the base substrate, and a side face of the electrode layer; and the material of the protective layer is an oxide of the first metal element.