An array substrate, a fabrication method thereof, and a display panel are provided. The array substrate comprises a substrate, and a plurality of thin-film-transistors, which includes an active layer formed on the substrate including a source region, a drain region, and a channel region located between the source region and the drain region, a source electrode metal contact layer, a drain electrode metal contact layer, a barrier layer formed on a side of the active layer facing away from the substrate, a source electrode formed on a side of the source electrode metal contact layer facing away from active layer, a drain electrode formed on a side of the drain electrode metal contact layer facing away from the active layer, and a gate electrode insulated from the barrier layer and formed on a side of the barrier layer facing away from the active layer.

Provided is a semiconductor device including electronic components electrically joined to each other via a metal nanoparticle sintered layer, wherein the metal nanoparticle sintered layer has formed therein a metal diffusion region in which a metal constituting a metallization layer formed on a surface of one of the electronic components is diffused, and in which the metal is present in an amount of 10 mass % or more and less than 100 mass % according to TEM-EDS analysis, and wherein the metal diffusion region has a thickness smaller than a thickness of the metallization layer.

Provided is a semiconductor device including electronic components electrically joined to each other via a metal nanoparticle sintered layer, wherein the metal nanoparticle sintered layer has formed therein a metal diffusion region in which a metal constituting a metallization layer formed on a surface of one of the electronic components is diffused, and in which the metal is present in an amount of 10 mass % or more and less than 100 mass % according to TEM-EDS analysis, and wherein the metal diffusion region has a thickness smaller than a thickness of the metallization layer.

A method for adjusting wafer deformation and a semiconductor structure are provided. The method includes the following operations. A deformation position and a deformation degree of a wafer are determined. At least one groove is formed at a back of the wafer according to the deformation position and the deformation degree. A stress film having a stress effect on the wafer deformation is formed at the back of the wafer with the at least one groove, and the stress film covers an inner wall of the at least one groove.

A method for adjusting wafer deformation and a semiconductor structure are provided. The method includes the following operations. A deformation position and a deformation degree of a wafer are determined. At least one groove is formed at a back of the wafer according to the deformation position and the deformation degree. A stress film having a stress effect on the wafer deformation is formed at the back of the wafer with the at least one groove, and the stress film covers an inner wall of the at least one groove.

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of high manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of high manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.

A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.

One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.