In one example, a workpiece support structure of a plasma treatment chamber has upper and lower ends, and first and second support members that extend between the upper and lower ends. The support members are electrically isolated from one another and offset from one another along a horizontal direction so as to define a cavity therebetween. The first and second support members support electrodes within the cavity such that (1) the electrodes are offset from one another along the vertical direction, (2) the electrodes extend between the first and second support members along the first horizontal direction, (3) a first set of the electrodes are electrically coupled to the first support member and electrically isolated from the second support member, and (4) a second set of the electrodes, different from the first set, are electrically coupled to the second support member and electrically isolated from the first support member.

According to one embodiment, there is provided a cleaning agent. The cleaning agent includes an azole-based compound having a group including at least one selected from the group consisting of a glycidyl group, a hydrolyzable silyl group, and an amino group.

According to one embodiment, an inspection method includes acquiring a first image based on a reflected light of a first light reflected by a surface of a leadframe when the first light is irradiated on the surface from a first direction. The inspection method further includes detecting a foreign matter at the surface by using the first image. The first direction is tilted with respect to the surface.

A method and processing system are provided for independent temperature and hydration control for an etching solution used for treating a wafer in process chamber. The method includes circulating the etching solution in a circulation loop, maintaining the etching solution at a hydration setpoint by adding or removing water from the etching solution, maintaining the etching solution at a temperature setpoint that is below the boiling point of the etching solution in the circulation loop, and dispensing the etching solution into the process chamber for treating the wafer. In one embodiment, the dispensing includes dispensing the etching solution into a processing region proximate the wafer in the process chamber, introducing steam into an exterior region that is removed from the wafer in the process chamber, and treating the wafer with the etching solution and the steam.

According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe. The leadframe may include: a plurality of pins extending from the center support structure; a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and a bar connecting the plurality of pins remote from the center support structure. The method may further include: bonding the IC chip to at least some of the plurality of pins; encapsulating the leadframe and bonded IC chip, including filling the groove with encapsulation compound; removing the encapsulation compound from the groove, thereby exposing at least a portion of the individual pins of the plurality of pins; plating the exposed portion of the plurality of pins; and cutting the IC package free from the bar by sawing through the encapsulated lead frame along the groove using a first saw width less than a width of the groove.

A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

A semiconductor chip is mounted at a first surface of a leadframe and an insulating encapsulation is formed onto the leadframe. An etching mask is applied to a second surface of the leadframe to cover locations of two adjacent rows of electrical contacts as well as a connecting bar between the two adjacent rows which electrically couples the electrical contacts. The second surface is then etched through the etching mask to remove leadframe material at the second surface and define the electrical contacts and connecting bar. The electrical contacts include a distal surface as well as flanks left uncovered by the insulating encapsulation. The etching mask is then removed and the electrical contacts and the connecting bars are used as electrodes in an electroplating of the distal surface and the flanks of the electrical contacts. The connecting bar is then removed from between the two adjacent rows during device singulation.

The present disclosure describes a method of forming an epitaxial layer on a substrate in a chamber. The method includes cleaning the chamber with a first etching gas and depositing the epitaxial layer on the substrate. Deposition of the epitaxial layer includes epitaxially growing a first portion of the epitaxial layer with a precursor, cleaning the substrate and the chamber with a flush of a second etching gas different from the first etching gas, and epitaxially growing a second portion of the epitaxial layer with the precursor. The first portion and the second portion have the same composition. The method furthers includes etching a portion of the epitaxial layer with a third etching gas having a flow rate higher than that of the second etching gas.

In examples, a method of forming a semiconductor package comprises forming a conversion coating solution comprising a salt of a vanadate, a salt of a zirconate, or both with a complexing agent; cleaning a copper lead frame, wherein the cleaned copper lead frame comprises copper oxide on an outer surface thereof; immersing the cleaned copper lead frame in the conversion coating solution; rinsing the copper lead frame; and forming an assembly by coupling a semiconductor die to the copper lead frame, coupling the semiconductor die to a lead of the copper lead frame, applying a mold compound onto at least a portion of the outer surface of the copper lead frame, and curing the mold compound. An adhesion strength at an interface between the mold compound and the at least the portion of the outer surface of the copper lead frame is increased relative to a same assembly formed without immersing the copper lead frame in the conversion coating solution.

According to an embodiment of the disclosure, a method of fabricating a carrier for a wafer level package (WLP) by using a lead frame, wherein the lead frame is fabricated by forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material, filling the first-half-etched surface with resin of an insulating material, removing the resin exposed to outside of the trench so that an upper surface of the trench and an upper surface of the resin are at a same level, and performing second half etching on a lower surface of the base substrate, in which a memory chip is attached to the lower surface of the base substrate.