The disclosure relates to a method of joining two semi-conductor substrates by molecular adhesion comprising: a step a) of bringing a first and a second substrate into intimate contact in order to form an assembly having a bonding interface; a step b) of reaction-annealing the bonding interface at a first temperature higher than a predetermined first temperature, this step b) generating bubbles at the joining interface; a step c) of at least partially debonding the two substrates at the bonding interface in order to eliminate the bubbles; and a step d) of bringing the first and the second substrate into intimate contact at the bonding interface in order to reform the assembly.

A method for manufacturing a semiconductor device includes implanting gas ions in a donor wafer and bonding the donor wafer to a carrier wafer to form a compound wafer. The method also includes subjecting the compound wafer to a thermal treatment to cause separation along a delamination layer and growing an epitaxial layer on a portion of separated compound wafer to form a semiconductor device layer. The method further includes cutting the carrier wafer.

A glass substrate has a compaction of 0.1 to 100 ppm. An absolute value |Δα.sub.50/100| of a difference between an average coefficient of thermal expansion α.sub.50/100 of the glass substrate and an average coefficient of thermal expansion of single-crystal silicon at 50° C. to 100° C., an absolute value |Δα.sub.100/200| of a difference between an average coefficient of thermal expansion α.sub.100/200 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 100° C. to 200° C., and an absolute value |Δα.sub.200/300| of a difference between an average coefficient of thermal expansion α.sub.200/300 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 200° C. to 300° C. are 0.16 ppm/° C. or less.

Methods for processing a semiconductor substrate are proposed. An example of a method includes forming cavities in the semiconductor substrate by implanting ions through a first surface of the semiconductor substrate. The cavities define a separation layer in the semiconductor substrate. A semiconductor layer is formed on the first surface of the semiconductor substrate. Semiconductor device elements are formed in the semiconductor layer. The semiconductor substrate is separated along the separation layer into a first substrate part including the semiconductor layer and a second substrate part.

Provided is an RF switch device and a method of manufacturing the same and, more particularly, to an RF switch device and a method of manufacturing the same seeking to improve RF characteristics by forming a trap layer on a part of the surface of a substrate, thereby trapping carriers that may accumulate on the surface of the substrate.

A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si.sub.1-xGe.sub.x, Si.sub.1-xC.sub.x, Si.sub.1-x-yGe.sub.xSn.sub.y, Si.sub.1-x-y-zGe.sub.xSn.sub.yC.sub.z, Ge.sub.1-xSn.sub.x, group IIIA-nitrides, semiconductor oxides, and any combination thereof.

A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.

Donor structures having a germanium buffer layer for preparing silicon-germanium-on-insulator structures by layer transfer are disclosed. Bonded structures and methods for preparing silicon-germanium-on-insulator structures by a layer transfer method are also disclosed.

An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RE devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.