A method includes forming a pad layer and a mask layer over a substrate; patterning the mask layer, the pad layer, and the substrate to form pads, masks, and first and semiconductor fins over the substrate; forming a liner covering the pads, the masks, and the first and second semiconductor fins; removing a first portion of the liner to expose sidewalls of the first semiconductor fin, while leaving a second portion of the liner covering sidewalls of the second semiconductor fin; forming an isolation material over the substrate; and performing a CMP process to the isolation material until a first one of the pads over the second semiconductor fin is exposed; and etching back the isolation material and the second portion of the liner.

A semiconductor device can include: a substrate having a first doping type; a first well region located in the substrate and having a second doping type, where the first well region is located at opposite sides of a first region of the substrate; a source region and a drain region located in the first region, where the source region has the second doping type, and the drain region has the second doping type; and a buried layer having the second doping type located in the substrate and below the first region, where the buried layer is incontact with the first well region, where the first region is surrounded by the buried layer and the first well region, and the first doping type is opposite to the second doping type.

A method can include ion implanting with the gate mask to form first halo regions and ion implanting with the gate mask and first spacers as a mask to form second halo regions. The gate mask and first spacers can be removed, and an epitaxial layer formed. A dummy gate mask can be formed. Ion implanting with the dummy gate mask can from source-drain extensions. Second spacers can be formed on sides of the dummy gate mask. Ion implanting with the dummy gate mask and second spacers as a mask can form source and drain regions. A surface dielectric layer can be formed and planarized to expose a top of the dummy gate. The dummy gate can be removed to form gate openings between the second spacers. A hi-K dielectric layer and at least two gate metal layers within the gate opening. Related devices are also disclosed.

A semiconductor device (1) according to an embodiment includes: a semiconductor substrate; a first well (15) formed on the semiconductor substrate; a second well (15) formed on the semiconductor substrate; first fins (11) formed in the first well; second fins (21) formed in the second well; and a first electrode (12a) connected to each of the first and second fins. The first well and the first fins (11) have the same conductivity type, and the second well and the second fins (21) have different conductivity types.

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a plurality of fins on a semiconductor substrate; forming an anti-diffusion layer, containing anti-diffusion ions, in the fins; forming an anti-punch through layer, containing anti-punch through ions, in the fins, a top surface of the anti-punch through layer being below a top surface of the anti-diffusion layer, and the anti-diffusion layer preventing the anti-punch through ions from diffusing toward tops of the fins; and performing a thermal annealing process.

The present disclosure relates to semiconductor devices, and more particularly, to high voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) and methods of manufacture. A structure of the present disclosure includes a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material including a first gate dielectric material and a second gate dielectric material, the second gate dielectric material including a thinner thickness than the first gate dielectric material, and a high-k dielectric material on the split-gate dielectric material.

The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

A semiconductor device structure includes a first S/D feature over a first device region of a substrate, a plurality of first semiconductor layers over the first device region of the substrate, and each first semiconductor layer is in contact with the first source/drain feature, a first gate electrode layer surrounding a portion of each first semiconductor layer, and a first dielectric spacer contacting the first S/D feature, the first dielectric spacer disposed between and in contact with two first semiconductor layers of the plurality of the first semiconductor layers. The substrate comprises a first dopant region underneath the first S/D feature and a second dopant region underneath first gate electrode layer and radial outwardly of the first dopant region, the first dopant region comprising first dopants having a first conductivity type and a first dopant concentration and the second dopant region comprising the first dopants having a second dopant concentration less than the first dopant concentration.

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type formed on the semiconductor substrate and having a first conductivity type impurity concentration higher than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type formed above the first semiconductor layer, a first device region formed in the second semiconductor layer and configured to operate based on a first reference voltage, a second device region formed in the second semiconductor layer and configured to operate based on a second reference voltage, the second device region being spaced apart from the first device region, and a region isolation structure interposed between the first and second device regions and formed in a region extending from a front surface of the second semiconductor layer to the first semiconductor layer so as to electrically isolate the first and second device regions from each other.