The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor; and a capacitor having a first conductive layer and a second conductive layer and disposed on a second region of the second nitride semiconductor layer. Wherein the first conductive layer of the capacitor and the first source electrode have a first material, and the second conductive layer of the capacitor and the first field plate have a second material.

The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor; and a capacitor having a first conductive layer and a second conductive layer and disposed on a second region of the second nitride semiconductor layer. Wherein the first conductive layer of the capacitor and the first source electrode have a first material, and the second conductive layer of the capacitor and the first field plate have a second material.

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.

A FET based double balanced mixer (DBM) that exhibits good conversion gain and IIP3 values and provides improved linearity and wide bandwidth. In one embodiment, a first balun is configured to receive a local oscillator (LO) signal and generate two balanced LO signals that are coupled to two corresponding opposing nodes of a four-node FET ring. A second balun is configured to pass an RF signal on the unbalanced side. The FET ring includes at least four FETs connected as branches of a ring, with the source of each FET connected to the drain of a next FET in the ring. Each FET is preferably fabricated as, or configured as, a low threshold voltage device having its gate connected to its drain, which causes the FET to operate as a diode, but with the unique characteristic of having close to a zero turn-on voltage.

A composite substrate includes a single crystal support substrate containing first element as a main component; an oxide single crystal layer provided on the single crystal support substrate and containing a second element (excluding oxygen) as a main component; and an amorphous layer provided in between the single crystal support substrate and the oxide single crystal layer and containing a first element, a second element, and Ar, the amorphous layer having a first amorphous region in which proportion of the first element is higher than proportion of the second element, and a second amorphous region in which the proportion of the second element is higher than the proportion of the first element, concentration of Ar contained in the first amorphous region being higher than concentration of Ar contained in the second amorphous region and being 3 atom % or more.

The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of the substrate by ion bombardment, wherein a plasma of a supplied gas is generated, and a bombardment energy of the ions in the plasma is controlled by a radio frequency electromagnetic field. The bombardment energy of the ions is higher than a first threshold so as to tear the metal contamination from the surface of the substrate, and the bombardment energy of the ions is lower than a second threshold so as to prevent a surface quality degradation of the surface of the substrate.

The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of the substrate by ion bombardment, wherein a plasma of a supplied gas is generated, and a bombardment energy of the ions in the plasma is controlled by a radio frequency electromagnetic field. The bombardment energy of the ions is higher than a first threshold so as to tear the metal contamination from the surface of the substrate, and the bombardment energy of the ions is lower than a second threshold so as to prevent a surface quality degradation of the surface of the substrate.

A substrate 10 comprises: a first layer L1 containing crystalline aluminum nitride; a second layer L2 containing crystalline α-alumina; and an intermediate layer Lm sandwiched between the first layer L1 and the second layer L2 and containing aluminum, nitrogen, and oxygen, and the content of nitrogen in the intermediate layer Lm decreases in a direction Z from the first layer L1 toward the second layer L2, and the content of oxygen in the intermediate layer Lm increases in the direction Z from the first layer L1 toward the second layer L2.

A nitride semiconductor device includes a first impurity layer made of an Al.sub.1-XGa.sub.XN (0<X≤1) based material and containing a first impurity with which a depth of an acceptor level from a valence band (E.sub.T-E.sub.V) is made not less than 0.3 eV but less than 0.6 eV, an electron transit layer formed on the first impurity layer, an electron supply layer formed on the electron transit layer, agate electrode formed on the electron transit layer, and a source electrode and a drain electrode formed such that the source electrode and the drain electrode sandwich the gate electrode and electrically connected to the electron supply layer.

A nitride semiconductor device includes a first impurity layer made of an Al.sub.1-XGa.sub.XN (0<X≤1) based material and containing a first impurity with which a depth of an acceptor level from a valence band (E.sub.T-E.sub.V) is made not less than 0.3 eV but less than 0.6 eV, an electron transit layer formed on the first impurity layer, an electron supply layer formed on the electron transit layer, agate electrode formed on the electron transit layer, and a source electrode and a drain electrode formed such that the source electrode and the drain electrode sandwich the gate electrode and electrically connected to the electron supply layer.