A semiconductor package is provided. The semiconductor package includes a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure including an insulating layer and a redistribution conductor provided in the insulating layer; a semiconductor chip provided on the rear surface and including a connection pad electrically connected to the redistribution conductor; an encapsulant provided on at least a portion of the semiconductor chip; under-bump metal (UBM) vias extending from the redistribution conductor to the front surface of the redistribution structure within the insulating layer; UBM pads provided on the front surface of the redistribution structure to correspond to the UBM vias, respectively, and each UMB pad of the UBM pads having an exposed surface convexly protruding away from the front surface of the redistribution structure; and a metal bump provided on the UBM pads and contacting the exposed surface of each UMB pad of the UBM pads.

A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

A printed structure includes a destination substrate comprising two or more contact pads disposed on or in a surface of the destination substrate, a component disposed on the surface, and two or more electrically conductive connection posts. Each of the connection posts extends from a common side of the component. Each of the connection posts is in electrical and physical contact with one of the contact pads. The component is tilted with respect to the surface of the destination substrate. Each of the connection posts has a flat distal surface.

An integrated circuit device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first insulating layer on the first surface of the semiconductor substrate, an electrode landing pad positioned on the first surface of the semiconductor substrate and having a sidewall surrounded by the first insulating layer, a top surface apart from the first surface of the semiconductor substrate, and a bottom surface opposite to the top surface, and a through-electrode configured to penetrate through the semiconductor substrate and contact the top surface of the electrode landing pad, wherein a horizontal width of the top surface of the electrode landing pad is less than a horizontal width of the bottom surface of the electrode landing pad and greater than a horizontal width of a bottom surface of the through-electrode in contact with the top surface of the electrode landing pad.

A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.

A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.