H01L2224/13216

Lead free solder columns and methods for making same
10937752 · 2021-03-02 · ·

Disclosed herein are embodiments of lead-free (Pb-free) or lead-bearing solder column devices that can include an inner core, an outer sleeve surrounding a portion of the inner core, at least one space along a length of the outer sleeve, and a second layer including a solder material coupled with a portion of the inner core within the at least one space. The inner core can be configured to support the solder column so as to prevent a collapse of the solder column at temperatures above a liquidus temperature of the outer sleeve's solder material and the second layer's solder material. The column serves as a heat-sink to conduct excessive heat away from a heat generating semiconductor chip. Moreover, the compliant solder column absorbs strain and mechanical stress caused by a difference in the coefficient of thermal expansion (CTE) connecting the semiconductor chip to a printed circuit board (PCB).

CHIP PACKAGE AND METHOD FOR FORMING THE SAME
20170256496 · 2017-09-07 ·

A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

CHIP PACKAGE AND METHOD FOR FORMING THE SAME
20170256496 · 2017-09-07 ·

A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.