A terminal structure includes a first wiring layer, an insulation layer covering the first wiring layer, an opening extending through the insulation layer and partially exposing the first wiring layer, a via wiring formed in the opening, a second wiring layer connected to the via wiring on the insulation layer, a protective metal layer on the second wiring layer, a solder layer covering the protective metal layer, and an intermetallic compound layer formed at an interface of the protective metal layer and the solder layer. The protective metal layer includes a projection projecting further outward from a side surface of the second wiring layer. The solder layer covers upper and side surfaces of the protective metal layer through the intermetallic compound layer and exposes a side surface of the second wiring layer. The intermetallic compound layer covers the upper and side surfaces of the protective metal layer.

The present invention discloses a package structure and a forming method thereof. The package structure includes a substrate and a redistribution layer. The redistribution layer includes a plurality of metal bumps distributed at intervals, at least the periphery of the metal bumps is covered with seed layers, and the seed layers of adjacent metal bumps are disconnected from each other. The seed layers of this embodiment have stable metallic characteristics, which may achieve effective protection of side walls of the metal bumps against metal-to-metal migration due to oxidation and corrosion of the metal bumps, thereby avoiding electrical leakage and failure of a chip and greatly increasing the reliability of the package structure.

An electrically conductive pillar that can bond a base member and a member to be bonded together with high bonding strength with a bonding layer interposed therebetween and a method for manufacturing the same. Specifically, an electrically conductive pillar 1 is composed of a sintered body 12 of metal micro-particles disposed on a base member 11. The average particle size of the metal micro-particles is less than 1 μm as measured using a small-angle X-ray scattering method. An upper surface 12b of the sintered body 12 has a concave shape recessed on the base member 11 side. The metal micro-particles are preferably made of one or more metals selected from Ag and Cu.

A fan-out wafer level package is disclosed, which includes: a redistribution layer; a semiconductor chip electrically connected with the redistribution layer through a bump; a protective member protecting the semiconductor chip, wherein a part of the protective member is removed such that the upper surface of the semiconductor chip is exposed in order to dissipate heat and prevent warpage; and an interconnector disposed outside the semiconductor chip at substantially the same level and having a lower part electrically connected with the redistribution layer and an upper part not being covered with the protective member, wherein the interconnector includes a metal core solder ball, the metal core solder ball includes a metal core and a solder buffer between the metal core and the protective member, and the metal core is formed of a combination of copper (Cu), nickel (Ni), and silver (Ag).

The disclosure is directed to an integrated circuit structure for joining wafers. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material.

The disclosure is directed to an integrated circuit structure for joining wafers. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material.

fan-out wafer level package is disclosed, which comprises: a redistribution layer; a semiconductor chip electrically connected with the redistribution layer through a bump; a protective member protecting the semiconductor chip, wherein a part of the protective member is removed such that the upper surface of the semiconductor chip is exposed in order to dissipate heat and prevent warpage; and an interconnector disposed outside the semiconductor chip at substantially the same level and having a lower part electrically connected with the redistribution layer and an upper part not being covered with the protective member, wherein the interconnector includes a metal core solder ball, the metal core solder ball includes a metal core and a solder buffer between the metal core and the protective member, and the metal core is formed of a combination of copper (Cu), nickel (Ni), and silver (Ag).