Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar. The die interconnect may also include a low wetting layer formed on the wetting barrier.

Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar such that during solder reflow, solder wetting of sidewall of the pillar is minimized or prevented all together. The die interconnect may also include a low wetting layer formed on the wetting barrier, which can further mitigate solder wetting problems.

In an embodiment, a device includes: a semiconductor substrate; a contact pad on the semiconductor substrate; a passivation layer on the contact pad and the semiconductor substrate; a die connector extending through the passivation layer, the die connector being physically and electrically coupled to the contact pad, the die connector including a first conductive material, the first conductive material being a Lewis acid having a first acid hardness/softness index; a dielectric layer on the die connector and the passivation layer; and a protective layer disposed between the dielectric layer and the die connector, the protective layer surrounding the die connector, the protective layer including a coordination complex of the first conductive material and an azole, the azole being a Lewis base having a first ligand hardness/softness index, where a product of the first acid hardness/softness index and the first ligand hardness/softness index is positive.

In an embodiment, a device includes: a semiconductor substrate; a contact pad on the semiconductor substrate; a passivation layer on the contact pad and the semiconductor substrate; a die connector extending through the passivation layer, the die connector being physically and electrically coupled to the contact pad, the die connector including a first conductive material, the first conductive material being a Lewis acid having a first acid hardness/softness index; a dielectric layer on the die connector and the passivation layer; and a protective layer disposed between the dielectric layer and the die connector, the protective layer surrounding the die connector, the protective layer including a coordination complex of the first conductive material and an azole, the azole being a Lewis base having a first ligand hardness/softness index, where a product of the first acid hardness/softness index and the first ligand hardness/softness index is positive.

A semiconductor device according to the present embodiment includes an insulation member, a columnar electrode, a member, and an electrode pad. The insulation member has a first face. The columnar electrode penetrates the insulation member in a direction approximately perpendicular to the first face. The columnar electrode has a columnar electrode member and a first metal layer of at least one layer which covers an outer circumference of the columnar electrode member and which extends until becoming exposed from the first face. The member is provided on the first face and is arranged so as to overlap with at least a part of the first metal layer that is exposed from the first face as viewed from a direction approximately perpendicular to the first face. The electrode pad is provided on the first face so as to cover the member and is electrically connected to the columnar electrode member.

A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.

A fan-out wafer level package is disclosed, which includes: a redistribution layer; a semiconductor chip electrically connected with the redistribution layer through a bump; a protective member protecting the semiconductor chip, wherein a part of the protective member is removed such that the upper surface of the semiconductor chip is exposed in order to dissipate heat and prevent warpage; and an interconnector disposed outside the semiconductor chip at substantially the same level and having a lower part electrically connected with the redistribution layer and an upper part not being covered with the protective member, wherein the interconnector includes a metal core solder ball, the metal core solder ball includes a metal core and a solder buffer between the metal core and the protective member, and the metal core is formed of a combination of copper (Cu), nickel (Ni), and silver (Ag).

fan-out wafer level package is disclosed, which comprises: a redistribution layer; a semiconductor chip electrically connected with the redistribution layer through a bump; a protective member protecting the semiconductor chip, wherein a part of the protective member is removed such that the upper surface of the semiconductor chip is exposed in order to dissipate heat and prevent warpage; and an interconnector disposed outside the semiconductor chip at substantially the same level and having a lower part electrically connected with the redistribution layer and an upper part not being covered with the protective member, wherein the interconnector includes a metal core solder ball, the metal core solder ball includes a metal core and a solder buffer between the metal core and the protective member, and the metal core is formed of a combination of copper (Cu), nickel (Ni), and silver (Ag).

A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.

A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.