A wiring substrate includes a first substrate and an electronic component mounted on an upper surface of the first substrate. A first pad is formed on an uppermost wiring layer of the first substrate. A connection terminal is formed on the electronic component and is located proximate to the first pad in a plan view. The wiring substrate further includes a connection member formed on the first pad to electrically connect the first pad and the connection terminal. The connection member includes a rod-shaped core and a solder layer, which is coated around the core and joined to the first pad. The solder layer includes a bulge that spreads from the core of the connection member in a planar direction. The bulge is joined to the connection terminal of the electronic component.

A wiring substrate includes a first substrate and an electronic component mounted on an upper surface of the first substrate. A first pad is formed on an uppermost wiring layer of the first substrate. A connection terminal is formed on the electronic component and is located proximate to the first pad in a plan view. The wiring substrate further includes a connection member formed on the first pad to electrically connect the first pad and the connection terminal. The connection member includes a rod-shaped core and a solder layer, which is coated around the core and joined to the first pad. The solder layer includes a bulge that spreads from the core of the connection member in a planar direction. The bulge is joined to the connection terminal of the electronic component.

A package to die connection system and method are provided. The system includes a semiconductor device having a substrate with a top surface. A gasket is affixed to the top surface of the substrate and has at least one cavity with a portion of the cavity open to a sidewall of the gasket. A semiconductor die is attached to the top surface of the substrate. A sidewall of the semiconductor die is abutted with the sidewall of the gasket. A portion of a metal layer is exposed to the open portion of the cavity. A pillar located in the cavity is electrically connected to the exposed portion of the metal layer.

Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at least a portion of the conductive seed layer, performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure, curing the deposited polymer material, and attaching a solder ball structure to a side of the conductive structure.

Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at least a portion of the conductive seed layer, performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure, curing the deposited polymer material, and attaching a solder ball structure to a side of the conductive structure.

A chip protection device includes a protection frame extending around side surfaces of a semiconductor chip mounted on a substrate. The protection frame includes a plurality of side walls, each wall facing and spaced apart from a respective side surface of the semiconductor chip, and a plurality of upper walls, each upper wall extending inward from an upper portion of a respective side wall toward the semiconductor chip. A plurality of apertures are formed through the side walls and through which a fluid enters and exits. The protection frame defines an inner space in which the fluid can flow via the plurality of apertures. Heat from the side surfaces of the semiconductor chip is transferred to the fluid in the inner space.

One or more electrical interconnects are formed beneath a device region within a volume of semiconductor material in which electronic devices are formed. The buried interconnects extended in a lateral direction parallel to surfaces of the die toward an edge of the semiconductor die. Such buried interconnects can be exposed at edges of the die to provide electrical contacts along those edges and can be coupled to electronic devices formed within the device region as alternatives to or in addition to contacts formed on top or bottom surfaces of the die.

A package structure includes a lead frame, an electronic device and a level-maintaining structure. The electronic device is disposed adjacent to the lead frame. The level-maintaining structure is disposed between the electronic device and the lead frame, and is configured to prevent the electronic device from tilting with respect to the lead frame. The electronic device includes at least one via protruding from a bottom surface of the electronic device.

A semiconductor device includes: a semiconductor element; a lead; a bonding target; a conductive bonding material that electrically bonds the bonding target and the lead; and a sealing resin that covers the bonding target and the lead. The lead includes a lead body including an obverse surface facing the bonding target, and a metal layer disposed on the obverse surface. A material of the metal layer has better wettability to the conductive bonding material in a molten state than a material of the lead body. The conductive bonding material is bonded to the metal layer. The obverse surface includes an uneven region spaced apart from the metal layer in plan view, and a smooth region located between the metal layer and the uneven region.

An electrode terminal of a semiconductor element includes a terminal portion and a pedestal portion. The terminal portion includes a terminal portion rear surface and a terminal portion side surface. The terminal portion side surface intersects with the terminal portion rear surface. The pedestal portion protrudes outwardly from a part of the terminal portion side surface of the terminal portion. The pedestal portion includes a pedestal portion rear surface, a pedestal portion side surface, and a curved surface. The pedestal portion rear surface is in contact with an insulating layer. The pedestal portion side surface intersects with the pedestal portion rear surface and is located outside the terminal portion side surface. The curved surface is disposed between the pedestal portion rear surface and the pedestal portion side surface.