A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

A semiconductor device includes a lead frame comprising a first terminal and a second terminal for grounding, a sealing resin which covers the lead frame, an exposed part which is a part of the second terminal and is exposed from the sealing resin and a conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part.

Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

An isolation system and isolation device are disclosed. An illustrative isolation device is disclosed to include a transmitter circuit to generate a first current in accordance with a first signal, a first elongated conducting element to generate a magnetic field when the first current flows through the first elongated conducting element, a second elongated conducting element adjacent to the first elongated conducting element so as to receive the magnetic field. The second elongated conducting element is configured to generate an induced current when the magnetic field is received. The receiver circuit is configured to receive the induced current as an input, and configured to generate a reproduced first signal as an output of the receiver circuit.

The present application provides a chip package structure and an electronic device, which could reduce a chip package thickness and implement ultra-thinning of chip package. The chip package structure includes a chip, a substrate, a lead and a lead protection adhesive; the lead is configured to electrically connect the chip and the substrate; the lead protection adhesive is configured to support the lead, where a highest point of the lead protection adhesive is not higher than a highest point of an upper edge of the lead.

A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.

A microelectronic device, in a fan-out fan-in chip scale package, has a die and an encapsulation material at least partially surrounding the die. Fan-out connections from the die extend through the encapsulation material and terminate adjacent to the die. The fan-out connections include wire bonds, and are free of photolithographically-defined structures. Fan-in/out traces connect the fan-out connections to bump bond pads. The die and at least a portion of the bump bond pads partially overlap each other. The microelectronic device is formed by mounting the die on a carrier, and forming the fan-out connections, including the wire bonds, without using a photolithographic process. The die and the fan-out connections are covered with an encapsulation material, and the carrier is subsequently removed, exposing the fan-out connections. The fan-in/out traces are formed so as to connect to the exposed portions of the fan-out connections, and extend to the bump bond pads.

A semiconductor module includes a substrate, a semiconductor die arranged on the substrate, at least one first bond wire loop, wherein both ends of the at least one first bond wire loop are arranged on and coupled to a first electrode of the semiconductor die, and a molded body encapsulating the semiconductor die, wherein a top portion of the at least one first bond wire loop is exposed from a first side of the molded body.

An integrated circuit package includes a transmission line structure, wire bonds, a first post and a second post. The transmission line structure runs from a printed circuit board (PCB) to an integrated circuit (IC) and includes a center transmission line between two ground lines and sealed from exposure to air. The wire bonds connect the transmission line structure to pads on the integrated circuit from where the center transmission line exits the integrated circuit package. The wire bonds are selected to have an impedance matched to impedance of the integrated circuit. The first post supports the center transmission line where the center transmission line enters the integrated circuit package from the printed circuit board. The second post supports the center transmission line where the center transmission line exits the integrated circuit package to connect to the wire bonds.

Various embodiments relate to a packaged radio frequency (RF) amplifier device implementing a split bondwire where the direct ground connection of an output capacitor is replaced with a set of bondwires connecting to ground in a direction opposite to the wires connecting to the output of a transistor to an output pad. This is done in order to reduce the effects of mutual inductance between the various bondwires associated with the output of the RF amplifier device.