A curved FPA comprises an array of detectors, with mesas etched between the detectors such that they are electrically and physically isolated from each other. Metallization deposited at the bottom of the mesas reconnects the detectors electrically and thereby provides a common ground between them. Strain induced by bending the FPA into a curved shape is across the metallization and any backfill epoxy, rather than across the detectors. Indium bumps are evaporated onto respective detectors for connection to a readout integrated circuit (ROIC). An ROIC coupled to the detectors is preferably thinned, and the backside of the ROIC may also include mesas such that the ROIC is reticulated.

A semiconductor device that has low power consumption and is capable of performing a product-sum operation is provided. The semiconductor device includes first and second cells, a first circuit, and first to third wirings. Each of the first and second cells includes a capacitor, and a first terminal of each of the capacitors is electrically connected to the third wiring. Each of the first and second cells has a function of feeding a current based on a potential held at a second terminal of the capacitor, to a corresponding one of the first and second wirings. The first circuit is electrically connected to the first and second wirings and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wiring changes and accordingly the amount of current of the first wiring changes from I1 to I3 and the amount of current of the second wiring changes from I2 to I4, the first circuit generates a current with an amount I1-I2-I3+I4. Note that the potential of the third wiring is changed by firstly inputting a reference potential to the third wiring and then inputting a potential based on internal data or a potential based on information obtained by a sensor.

The present invention provides a method of forming a metal grid, a backside illuminated (BSI) image sensor, and a method of forming the BSI image sensor. In the methods, an etch stop layer and a metal material layer are successively deposited in geometric conformity over a substrate already formed therein with a recess and a conductive pillar, followed by the formation of a bonding pad on the metal material layer in the recess. After that, a dielectric cap layer is deposited and etched together with the metal material layer and the etch stop layer to form the metal grid. According to the present invention, the deposited metal material layer has reduced surface roughness, which results in improved thickness uniformity of the resulting metal grid. The metal grid is overall easier to form, resulting in savings in cost and increased performance of the device being fabricated.

A pulse-width modulation (PWM) image sensor is described herein. The PWM image sensor may have a stacked configuration. A top wafer of the PWM image sensor may have a charge-to-time converter and a logic wafer, stacked with the top wafer, may include a time-to-digital converter. The PWM image sensor may utilize variable transfer functions to avoid highlight compression and may utilize non-linear time quantization. A threshold voltage, as input to a charge-to-time converter, may additionally be controlled to affect light detection, dynamic range, and other features associated with the PWM image sensor.

An image sensor comprises a first and second chips. The first chip includes a first semiconductor substrate, a photoelectric conversion layer in the first semiconductor substrate, a color filter, a micro lens, a first transistor adjacent to the photoelectric conversion layer, a first insulating layer, and a first metal layer in the first insulating layer and connected to the first transistor. The second chip includes a second insulating layer, a second semiconductor substrate, a second transistor on the second semiconductor substrate, a second metal layer in the second insulating layer and connected to a gate structure of the second transistor through a gate contact, a landing metal layer below the second metal layer, and a through via in direct contact with the landing metal layer and vertically passing through the second semiconductor substrate. A width of the through via becomes narrower as the width approaches the third surface.

A solid-state imaging element including a well improves area efficiency while reducing malfunction of a circuit on the well. The solid-state imaging element includes a first well, a second well, a first circuit, and a second circuit. The first well contains an impurity having a polarity identical to a polarity of an impurity in a substrate. The second well contains an impurity having a polarity identical to the polarity of the impurity in the substrate and is disposed adjacent to the first well. The first circuit is disposed on the first well and generates noise in a predetermined period. The second circuit is disposed on the second well and generates noise in a period different from the predetermined period.

An imaging apparatus with reduced flare includes an imaging structure including a solid state imaging element (1) and a transparent substrate (2) disposed on the imaging element. The imaging apparatus includes a circuit substrate (7) including a circuit, a spacer (10) including at least one fixing portion (11) that guides the imaging structure to a desired position on the circuit substrate (7) when the imaging structure is mounted on the circuit substrate, and a light absorbing material (13) disposed on at least one side surface of the imaging structure such that that light absorbing material (13) is between the imaging structure and the at least one fixing portion.

A solid-state imaging device includes a first and second pixel regions. In the first pixel region, a photoelectric conversion unit, a floating diffusion region (FD), and a transferring transistor are provided. In the second pixel region, an amplifying transistor, and a resetting transistor are provided. A first element isolation portion is provided in the first pixel region, while a second element isolation portion is provided in the second pixel region. An amount of protrusion of an insulating film into a semiconductor substrate in the first element isolation portion is smaller, than that in the second element isolation portion.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.